參數(shù)資料
型號: KSZ8051MLL TR
廠商: Micrel Inc
文件頁數(shù): 8/48頁
文件大?。?/td> 0K
描述: TXRX PHY 10/T100 3.3V MII 48LQFP
標準包裝: 1,000
類型: PHY 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: MII
電源電壓: 1.8V,2.5V,3.3V
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
配用: 576-3864-ND - BOARD EVALUATION FOR KSZ8051MLL
Micrel, Inc.
KSZ8051MLL
July 2010
16
M9999-071210-1.0
Figure 1. Auto-Negotiation Flow Chart
MII Data Interface
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
10Mbps and 100Mbps data rates are supported at both half and full duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 4-bit wide, a nibble.
By default, the KSZ8051MLL is configured to MII mode after it is powered up or hardware reset with the following:
A 25MHz crystal connected to XI, XO (pins 15, 14), or an external 25MHz clock source (oscillator) connected to
XI.
The CONFIG[2:0] strapping pins (pins 27, 41, 40) set to ‘000’ (default setting).
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