參數(shù)資料
型號: KSZ8842-32MVLI
廠商: Micrel Inc
文件頁數(shù): 4/141頁
文件大?。?/td> 0K
描述: IC SWITCH ETH 2P 32BIT 128LQFP
標(biāo)準(zhǔn)包裝: 90
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1635-ND - BOARD EVALUATION KSZ8842-16MVL
其它名稱: 576-3270
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
101
M9999-102207-1.9
Bank 48 Port 1 VID Control Register (0x04): P1VIDCR
This register contains the global per port control for the switch function.
Bit
Default
R/W
Description
15-13
0x0
RW
Default Tag[15:13]
Port’s default tag, containing “User Priority Field” bits.
12
0
RW
Default Tag[12]
Port’s default tag, containing CFI bit.
11-0
0x001
RW
Default Tag[11:0]
Port’s default tag, containing VID[11:0].
Note: This VID Control register serves two purposes:
1. Associated with the ingress untagged packets, and used for egress tagging.
2. Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.
Bank 48 Port 1 Control Register 3 (0x06): P1CR3
Bit
Default
R/W
Description
15-5
0x000
RO
Reserved
4
0x0
RW
Reserved
3-2
0x0
RW
Ingress Limit Mode
These bits determine what kinds of frames are limited and counted against Ingress
limiting as follows:
00 = Limit and count all frames.
01 = Limit and count Broadcast, Multicast, and flooded unicast frames.
10 = Limit and count Broadcast and Multicast frames only.
11 = Limit and count Broadcast frames only.
1
0
RW
Count IFG
Count IFG Bytes.
1= each frame’s minimum inter frame gap.
(IFG) bytes (12 per frame) are included in Ingress and Egress rate limiting
calculations.
0= IFG bytes are not counted.
0
RW
Count Preamble
Count preamble Bytes.
1 = each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate
limiting calculations.
0 = preamble bytes are not counted.
相關(guān)PDF資料
PDF描述
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