參數(shù)資料
| 型號： | KSZ8842-32MVLI |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 75/141頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH ETH 2P 32BIT 128LQFP |
| 標準包裝： | 90 |
| 控制器類型： | 以太網開關控制器 |
| 接口： | PCI |
| 電源電壓： | 3.1 V ~ 3.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1635-ND - BOARD EVALUATION KSZ8842-16MVL |
| 其它名稱： | 576-3270 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁當前第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
39
M9999-102207-1.9
BE2N, BE1N, and BE0N are ignored as shown in the Figure 19. No other registers can be accessed by asserting
DATACSN. The data transfer is the same as in the first case. Independent of the type of asynchronous interface
used. To insert a wait state, the BIU will assert ARDY to prolong the cycle.
Synchronous Interface
For synchronous transfers, the synchronous dedicated signals CYCLEN, SWR, and RDYRTNN will toggle but the
asynchronous dedicated signals RDN and WRN are de-asserted and stay at the same logic level throughout the entire
synchronous transfer.
The synchronous interface mainly supports two applications, one for VLBus-like and the other for EISA-like (DMA type C)
burst transfers. The VLBus-like interface supports only single-data transfer. The pin option VLBUSN determines if it is a
VLBus-like or EISA-like burst transfer – if VLBUSN = 0, the interface is for VLBus-like transfer; if VLBUSN = 1, the
interface is for EISA-like burst transfer.
For VLBus-like transfer interface (VLBUSN = 0):
This interface is used in an architecture in which the device’s local decoder is utilized; that is, the BIU decodes latched
A [15:4] and qualifies with AEN (Address Enable) to determine if the switch is the intended target. No burst is
supported in this application. The M/nIO signal connection in VLBus is routed to AEN. The CYCLEN in this application
is used to sample the SWR signal when it is asserted. Usually, CYCLEN is one clock delay of ADSN. There is a
handshaking process to end the cycle of VLBus-like transfers. When the KSZ8842M is ready to finish the cycle, it
asserts SRDYN
. The system/host acknowledges SRDYN by asserting RDYRTNN after the system/host has latched
the read data. The KSZ8842M holds the read data until RDYRTNN is asserted. The timing waveform is shown in
Figures 23 and 24.
For EISA-like burst transfer interface (VLBUSN = 1):
The SWR is connected to IORC# in EISA to indicate the burst read and CYCLEN is connected to IOWC# in EISA to
indicate the burst write. Note that in this application, both the system/host/memory and KSZ8842M are capable of
inserting wait states. For system/host/memory to insert a wait state, assert the RDYRTNN signal; for the KSZ8842M
to insert the wait state, assert the SRDYN signal. The timing waveform is shown in Figures 21 and 22.
Summary
Figure 12 shows the mapping from ISA-like, EISA-like and VLBus-like transactions to the switch’s BIU.
Figure 13 shows the connection for different data bus sizes.
For detail 8/16-bit bus signal connections and descriptions refers to Application Note 132.
For detail 32-bit bus signal connections and descriptions refers to Application Note 137.
Note: For the 8-bit data bus mode, the internal inverter is enabled and connected between BE0N and BE1N, so even
address will enable the BE0N and odd address will enable the BE1N.
相關PDF資料 |
PDF描述 |
|---|---|
| KSZ8842-PMBL AM TR | IC ETHERNET SW 2PORT 100LFBGA |
| KSZ8842-PMQLI | IC ETHERNET SW 2PORT PCI 128PQFP |
| KSZ8851-16MLLI TR | IC MAC CTLR 1PORT W/BUS 48LQFP |
| KSZ8851-16MLLJ | IC CTLR MAC 1PORT NON-PCI 48LQFP |
| KSZ8851-32MQLI | IC CTLR MAC/PHY NON PCI 128PQFP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8842-MQL | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface |
| KSZ8842P | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with PCI Interface |
| KSZ8842-PMBL | 功能描述:以太網 IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface (Lead Free) RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842-PMBL AM | 功能描述:以太網 IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface(Lead Free) RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842-PMBL AM TR | 功能描述:以太網 IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface(Lead Free) RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。