參數(shù)資料
型號: KSZ8893FQL
廠商: Micrel Inc
文件頁數(shù): 51/117頁
文件大?。?/td> 0K
描述: IC SWITCH FAST ETH 3PORT 128PQFP
標準包裝: 66
控制器類型: 以太網(wǎng)開關控制器
接口: MII,RMII,SNI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應商設備封裝: 128-PQFP(14x20)
包裝: 托盤
配用: 576-1603-ND - EVAL KIT EXPERIMENTAL KSZ8893MQL
其它名稱: 576-1565
Micrel, Inc.
KSZ8893FQL
October 2007
39
M9999-101607-1.3
The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at one-quarter the
network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error has
occurred during transmission. Similarly, the receive side has signals that convey when the data is valid and without
physical layer errors. For half-duplex operation, the SCOL signal indicates if a collision has occurred during
transmission.
The KSZ8893FQL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC mode
operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a
transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the
KSZ8893FQL. So, for PHY mode operation, if the device interfacing with the KSZ8893FQL has an MRXER input pin, it
needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8893FQL has an MTXER
input pin, it also needs to be tied low.
RMII Interface Operation
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII
provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
1. Supports 10Mbps and 100Mbps data rates.
2. Uses a single 50 MHz clock reference (provided externally).
3. Provides independent 2-bit wide (di-bit) transmit and receive data paths.
4. Contains two distinct groups of signals: one for transmission and the other for reception
The RMII provided by the KSZ8893FQL is connected to the device’s third MAC. It complies with the RMII Specification.
The following table describes the signals used by the RMII bus. Refer to RMII Specification for full detail on the signal
description.
RMII
Signal Name
Direction
(with respect
to the PHY)
Direction
(with respect
to the MAC)
RMII
Signal Description
KSZ8893FQL RMII
Signal (direction)
REF_CLK
Input
Input or
Output
Synchronous 50 MHz clock
reference for receive, transmit
and control interface
REFCLK (input)
CRS_DV
Output
Input
Carrier sense/
Receive data valid
SMRXDV (output)
RXD1
Output
Input
Receive data bit 1
SMRXD[1] (output)
RXD0
Output
Input
Receive data bit 0
SMRXD[0] (output)
TX_EN
Input
Output
Transmit enable
SMTXEN (input)
TXD1
Input
Output
Transmit data bit 1
SMTXD[1] (input)
TXD0
Input
Output
Transmit data bit 0
SMTXD[0] (input)
RX_ER
Output
Input
(not required)
Receive error
(not used)
---
SMTXER* (input)
* Connects to RX_ER
signal of RMII PHY device
Table 9. RMII Signal Description
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