參數(shù)資料
型號: KSZ8893FQL
廠商: Micrel Inc
文件頁數(shù): 62/117頁
文件大?。?/td> 0K
描述: IC SWITCH FAST ETH 3PORT 128PQFP
標準包裝: 66
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII,RMII,SNI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應商設備封裝: 128-PQFP(14x20)
包裝: 托盤
配用: 576-1603-ND - EVAL KIT EXPERIMENTAL KSZ8893MQL
其它名稱: 576-1565
Micrel, Inc.
KSZ8893FQL
October 2007
49
M9999-101607-1.3
4. Read back and verify the register settings in the KSZ8893FQL, using the I
2C read operation.
5. Write a ‘1’ to the “Start Switch” bit to start the KSZ8893FQL with the programmed settings.
Note:
The “Start Switch” bit cannot be set to ‘0’ to stop the switch after a ‘1’ is written to this bit. Thus, it is
recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power
down” can be programmed after the switch has been started.
SPI Slave Serial Bus Configuration
In managed mode, the KSZ8893FQL can be configured as a SPI slave device. In this mode, a SPI master device
(external controller/CPU) has complete programming access to the KSZ8893FQL’s 142 registers. Programming access
includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the “Static MAC
Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are indirectly accessed via
registers 121 to 131.
The KSZ8893FQL supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data write.
SPI multiple read and multiple write are also supported by the KSZ8893FQL to expedite register read back and register
configuration, respectively.
SPI multiple read is initiated when the master device continues to drive the KSZ8893FQL SPIS_N input pin (SPI Slave
Select signal) low after a byte (a register) is read. After the read, the KSZ8893FQL’s internal address counter
increments automatically to the next byte (next register). The next byte at the next register address is shifted out onto
the KSZ8893FQL SPIQ output pin. SPI multiple read continues until the SPI master device terminates it by de-asserting
the SPIS_N signal to the KSZ8893FQL.
Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8893FQL SPIS_N input pin
low after a byte (a register) is written. The KSZ8893FQL internal address counter increments automatically to the next
byte (next register) after the write. The next byte that is sent from the master device to the KSZ8893FQL SDA input pin
is written to the next register address. SPI multiple write continues until the SPI master device terminates it by de-
asserting the SPIS_N signal to the KSZ8893FQL.
For both SPI multiple read and multiple write, the KSZ8893FQL internal address counter wraps back to register address
zero once the highest register address is reached. This feature allows all 142 KSZ8893FQL registers to be read, or
written with a single SPI command from any initial register address.
The KSZ8893FQL is capable of supporting a 5MHz SPI bus.
The following is a sample procedure for programming the KSZ8893FQL using the SPI bus:
1. At the board level, connect the KSZ8893FQL pins as follows:
KSZ8893FQL Pin #
KSZ8893FQL Signal Name
External Processor Signal Description
99
SPIS_N
SPI Slave Select
97
SCL
(SPIC)
SPI Clock
98
SDA
(SPID)
SPI Data
(Master output; Slave input)
96
SPIQ
SPI Data
(Master input; Slave output)
Table 20. KSZ8893FQL SPI Connections
2. Enable SPI slave mode by setting the KSZ8893FQL strap-in pins PS[1:0] (pins 100 and 101, respectively) to
“10”.
3. Power up the board and assert reset to the KSZ8893FQL.
After reset, the “Start Switch” bit (register 1 bit [0]) is set to ‘0’.
4. Configure the desired register settings in the KSZ8893FQL, using the SPI write or multiple write command.
5. Read back and verify the register settings in the KSZ8893FQL, using the SPI read or multiple read command.
6. Write a ‘1’ to the “Start Switch” bit to start the KSZ8893FQL with the programmed settings.
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