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參數(shù)資料
| 型號： | L8574D |
| 英文描述： | CAP 15PF 50V 5% C0G SMD-0402 TR-7-PA SN100 |
| 中文描述： | L8574D電阻用戶線接口電路（SLIC），環(huán)繼電器和保護(hù)（SRP）的為遠(yuǎn)距離和TR - 57應(yīng)用 |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 489K |
| 代理商： | L8574D |
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14
Lucent Technologies Inc.
Data Sheet
October 1998
Relay, and Protector (SRP) for Long Loop and TR-57 Applications
L8574D Resistive Subscriber Line Interface Circuit (SLIC), Ring
Electrical Characteristics
(continued)
Data Interface and Logic
Table 9. Logic Inputs (CE, CS, and B0—B3) and Output NSTAT
1.Unless otherwise specified, all logic voltages are referenced to DGND.
2.This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 10. Timing Requirements (B0—B3 and CS)
A low-to-high transition on pin CS latches the data on pins B0—B3 into the device. When CS is either high or low,
the device is unaffected by data on pins B0—B3. The status of the thermal shutdown circuit is output on B3 when
CS is high (thermal shutdown is a logic 0). A low on channel enable lead CE asynchronously resets the data latch
to 1111 (scan state with the relay driver off) and disables CS so that CS cannot latch any data into the device. A
high on CE enables CS.
1.Unless otherwise specified, all times are measured from the 50% point of logic transitions.
2.These parameters are not tested in production. They are guaranteed by design and device characterization.
Table 11. Relay Driver (RDO)
The relay driver output RDO is low (relay operated) when a low input on B3 is latched into the device.
1.Unless otherwise specified, all logic voltages are referenced to DGND.
2.This parameter is not tested in production. It is guaranteed by design and device characterization.
Parameter
1
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
I
OSS
C
OL
Min
2
0
—
Max
V
DD
0.8
±
10
V
DD
0.4
35
50
Unit
V
V
μ
A
V
V
mA
pF
High-level Input Voltage
Low-level Input Voltage
Input Bias Current (high and low)
High-level Output Voltage (I
OUT
= –100
μ
A)
Low-level Output Voltage (I
OUT
= 180
μ
A)
Output Short-circuit Current (V
OUT
= V
DD
)
Output Load Capacitance
2
V
DD
– 1.5
0
1
0
Parameter
1, 2
Symbol
t
R
, t
F
C
IN
t
SDS
t
HDS
t
WCS
Min
0
—
150
50
225
Max
50
5
—
—
—
Unit
ns
pF
ns
ns
ns
CS Rise and Fall Time (10% to 90%)
Maximum Input Capacitance
Minimum Setup Time from B0—B3 Valid to CS
Minimum Hold Time from CS to B0—B3 Not Valid
Minimum Pulse Width of CS
Parameter
1
Symbol
I
OFF
V
ON
V
ON
I
R
V
OC
t
ON
t
OFF
Min
—
0
0
—
V
DD
—
—
Max
±
10
1.0
0.40
±
10
Unit
μ
A
V
V
μ
A
V
μ
s
μ
s
Off-state Output Current (V
RDO
= V
DD
)
On-state Output Voltage (I
RDO
= 70 mA)
On-state Output Voltage (I
RDO
= 20 mA)
Clamp Diode Reverse Current (V
RDO
= 0)
Clamp Diode On Voltage (I
RDO
= 150 mA)
Turn-on Time
2
Turn-off Time
2
V
DD
+ 2.0
10
10
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