參數(shù)資料
型號(hào): L8574D
英文描述: CAP 15PF 50V 5% C0G SMD-0402 TR-7-PA SN100
中文描述: L8574D電阻用戶線接口電路(SLIC),環(huán)繼電器和保護(hù)(SRP)的為遠(yuǎn)距離和TR - 57應(yīng)用
文件頁(yè)數(shù): 26/36頁(yè)
文件大?。?/td> 489K
代理商: L8574D
26
Lucent Technologies Inc.
Data Sheet
October 1998
Relay, and Protector (SRP) for Long Loop and TR-57 Applications
L8574D Resistive Subscriber Line Interface Circuit (SLIC), Ring
Applications
(continued)
On-Hook Transmission
During the on-hook transmission and talk/on-hook
transmission states, the L8574 provides 750
μ
A dc bias
current out of the Tip/Ring current driver amplifiers.
This creates a dc voltage drop across the external 19.6
k
resistors, R
BIAS1
and R
BIAS2
, which provides suffi-
cient dc bias to support on-hook transmission. The
switchhook detector is adjusted to compensate for this
dc bias current. The L8574 is able to support on-hook
transmission to drive a 3.17 dBm signal into a 600
or
900
ac loop. The capacitors, C
BIAS1
and C
BIAS2
, pro-
vide an ac path so transmission is not distorted by
R
BIAS1
and R
BIAS2
. Zener diode, D
SPEED
, reduces the
settling time transition from on- to off-hook.
Parallel Data Interface
A 6-wire parallel interface (CE, CS, B0, B1, B2, and B3)
is used to pass control information from the control
logic on the line card to the L8574. The L8574 has
eight operating states. These states are selected using
three logic input bits, B0—B2, according to the truth
table shown in Table 14. Logic input B3 operates a
relay driver independent of the state of bits B0—B2.
Data on the parallel data bus, B0—B3, is loaded into a
4-bit latch on the L8574 on the low-to-high transition of
the channel select lead CS. Changes in the data at
inputs B0—B3 do not affect the L8574 while CS is
either low or high. A low on channel enable lead CE
asynchronously resets the 4-bit latch to 1111 (scan
state with the relay driver off) and disables the channel
select lead CS (i.e., CS is prevented from loading any
data into the 4-bit latch). A high on CE enables CS.
State transitions and delays between transitions are left
to the discretion of the user since, except for fault con-
ditions, the state of the L8574 depends only on the
external control provided through the logic interface.
Supervision
The L8574 offers the ring trip, loop closure, and ther-
mal shutdown functions. The status of these functions
are provided as device outputs. The outputs of the ring
trip and off-hook supervision detectors are multiplexed
into a single output called NSTAT. The device state
determines which output is connected to NSTAT. The
device state table, Table 14, details which supervision
output (loop closure or ring trip) is seen at NSTAT dur-
ing a given device state.
Detector values are independent of office battery and
are valid over the entire range of V
BAT1
and V
BAT2
. How-
ever, NSTAT must indicate an on-hook (NSTAT = 1) if
either V
BAT1
or V
BAT2
is disconnected (open circuit) from
its dc source and an off-hook (NSTAT = 0) if the L8574
is in thermal shutdown. V
BAT1
and V
BAT2
are defined as
disconnected depending on the voltage at the power
supply pins as follows (the pins of supplies which have
more than one pin are shorted together):
If V
BAT1
–20 V (i.e., more negative than –20 V) and
V
BAT2
–20 V, then NSTAT must operate normally.
If V
BAT1
–10 V (i.e., more positive than –10 V) or V
BAT2
–10 V, then NSTAT must be on-hook (NSTAT = 1).
The status of the thermal shutdown circuit is output on
B3 when CS is high (thermal shutdown = 0 V).
Off-Hook Detection
The off-hook or loop closure threshold on the L8574
SLIC is internally fixed. Off-hook is indicated (NSTAT =
0) if the loop resistance is a maximum 2700
. On-
hook is indicated (NSTAT = 1) if the loop resistance is a
minimum 4400
.
Ring Trip
The ring trip threshold is set by resistor R
10
in the resis-
tor module. With R
10
set to 600
, the circuit is guaran-
teed to ring trip up to 1840
. With a 20 Hz ringing
source, the trip time is guaranteed less than 200 ms.
The ring trip circuit assumes uses of battery-backed
ringing. Pretrip immunity is such that a load across
Tip and Ring of 10 k
in parallel with an 8
μ
F capacitor
will not cause ring trip. Three external components
are required for ring trip, a 1 M
resistor from R
TS
to
V
BF
, resistor R
10
, which is a 600
resistor from R
SW
to V
BF
, and a 0.1
μ
F capacitor from R
SW
to R
TS
. The
components required for ring trip circuit are shown in
Figure 9. Note that R
10
is implemented in the resistor
module. All other components are discrete.
5-5276 (F)
Figure 9. Ring Trip Threshold
600
R
10
1 M
RTS
RSW
V
BF
0.1
μ
F
L8574
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