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參數(shù)資料
| 型號(hào)： | L8574D |
| 英文描述： | CAP 15PF 50V 5% C0G SMD-0402 TR-7-PA SN100 |
| 中文描述： | L8574D電阻用戶線接口電路（SLIC），環(huán)繼電器和保護(hù)（SRP）的為遠(yuǎn)距離和TR - 57應(yīng)用 |
| 文件頁數(shù)： | 31/36頁 |
| 文件大小： | 489K |
| 代理商： | L8574D |
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Data Sheet
October 1998
Lucent Technologies Inc.
31
Relay, and Protector (SRP) for Long Loop and TR-57 Applications
L8574D Resistive Subscriber Line Interface Circuit (SLIC), Ring
ac Design
(continued)
Design Equations
(continued)
Using the circuit of Figure 12, the ratio of capacitors C
T
and C
R
will affect the (transmit and receive) gain flatness,
and to a lesser degree the return loss of the line circuit. Thus, depending on the requirements, C
T
and C
R
may need
to be tight tolerance capacitors.
If this is the case, capacitors C
T
and C
R
may be combined into a single capacitor with a looser tolerance. This is
illustrated in Figure 13.
12-3426.a(F).r3
Figure 13. Revised ac Interface C
T
and C
R
Combined into a Single Capacitor C
S
XMT
R
T2
C
T
IRP
C
R
V
F
R
O
R
RV2
XMT
R
T2
IRP
C
S
= C
T
+ C
R
V
F
R
O
R
RV2
R
RV1
R
RV1
—
To scale C
S
(higher), increase C
T
(and decrease R
T2
)
by increasing the R
GX1
/(R
GX1
+ R
T1
) ratio by rearrang-
ing the circuit in Figure 13 and by adding resistor R
SC
from XMT to IRP as shown below.
12-3427.abF)
Figure 14. Addition of Resistor R
SC
from XMT to IRP
Then,
Once the gains and complex termination are set, if the
hybrid balance network is identical to the termination
impedance, then the hybrid balance is set by a single
resistor (shown in Figure 12) and is computed as fol-
lows:
R
K
TX
K
RCV
×
The L8574 SLIC is ground referenced. However, a +5 V
only codec, such as T7504, is referenced to +2.5 V. The
L8574 SLIC has sufficient dynamic range to accommo-
date an ac signal from the codec that is referenced to
+2.5 V without clipping distortion. Furthermore, a dc
current will flow between the L8574 SLIC and +5 V only
codec. With the L8574 SLIC, this current will not affect
ac performance, but it does waste power. To avoid
wasted power consumption, blocking capacitors can be
added. Capacitors should be placed to block any path
from any low impedance +2.5 V biased node on the
T7504 codec (or other +5 V only codec) to the SLIC. A
blocking capacitor (C
B
) has been added in the applica-
tion drawing in Figure 14.
After the blocking capacitor C
B
is added, the above
component values may have to be adjusted slightly to
optimize performance.
The effects of the blocking capacitor are best evaluated
and optimized by circuit simulation. Contact your
Lucent Technologies Microelectronics Group Account
Manager for information on availability of a PSPICE*
model.
*PSPICEis a registered trademark of MicroSim Corporation.
R
T1
R
SC
IRP
C
T
R
T2
XMT
VRN
R
GX1
C
B
VF
X
IN
R
R
GX1
R
T1
+
-----------------------------
||
------------------------------------
)
1
400
---------
1
1
′
---------
–
R
+
R
RV1
R
SC
------------------------------
+
=
R
HB
----------------------------
=
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