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參數(shù)資料
| 型號(hào)： | LAMXO640C-3TN100E |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 17/77頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA AUTO 640LUTS 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | LA-MachXO |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 4.9ns |
| 電壓電源 - 內(nèi)部： | 1.71 V ~ 3.465 V |
| 宏單元數(shù)： | 320 |
| 輸入/輸出數(shù)： | 74 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 220-1639 LAMXO640C-3TN100E-ND |
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2-21
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
with the rest of the system. These capabilities make the LA-MachXO ideal for many multiple power supply and
hot-swap applications.
Sleep Mode
The LA-MachXO “C” devices (VCC = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced
dramatically during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin.
During Sleep mode, the logic is non-operational, registers and EBR contents are not maintained, and I/Os are tri-
stated. Do not enter Sleep mode during device programming or conguration operation. In Sleep mode, power sup-
plies are in their normal operating range, eliminating the need for external switching of power supplies. Table 2-11
compares the characteristics of Normal, Off and Sleep modes.
Table 2-11. Characteristics of Normal, Off and Sleep Modes
SLEEPN Pin Characteristics
The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the
device. This pin also has a weak pull-up, along with a Schmidt trigger and glitch lter to prevent false triggering. An
external pull-up to VCC is recommended when Sleep Mode is not used to ensure the device stays in normal oper-
ation mode. Typically, the device enters sleep mode several hundred nanoseconds after SLEEPN is held at a valid
low and restarts normal operation as specied in the Sleep Mode Timing table. The AC and DC specications por-
tion of this data sheet shows a detailed timing diagram.
Oscillator
Every LA-MachXO device has an internal CMOS oscillator. The oscillator can be routed as an input clock to the
clock tree or to general routing resources. The oscillator frequency can be divided by internal logic. There is a ded-
icated programming bit to enable/disable the oscillator. The oscillator frequency ranges from 16MHz to 26MHz.
Conguration and Testing
The following section describes the conguration and testing features of the LA-MachXO automotive family of
devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LA-MachXO devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test
access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verication. The test
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with
one of the VCCIO Banks (LA-MachXO256: VCCIO1; LA-MachXO640: VCCIO2; LA-MachXO1200 and LA-
MachXO2280: VCCIO5) and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Characteristic
Normal
Off
Sleep
SLEEPN Pin
High
—
Low
Static Icc
Typical <10mA
0
Typical <100uA
I/O Leakage
<10A
<1mA
<10A
Power Supplies VCC/VCCIO/VCCAUX
Normal Range
0
Normal Range
Logic Operation
User Dened
Non Operational
Non operational
I/O Operation
User Dened
Tri-state
JTAG and Programming circuitry
Operational
Non-operational
EBR Contents and Registers
Maintained
Non-maintained
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LAMXO640C-3TN144E | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Auto Grade (AEC-Q100 ) MachXO640C RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LAMXO640E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet |
| LAMXO640E-3FTN256E | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Auto Grade (AEC-Q100 ) MachXO640E RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LAMXO640E-3TN100E | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Auto Grade (AEC-Q100 ) MachXO640E RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LAMXO640E-3TN144E | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Auto Grade (AEC-Q100 ) MachXO640E RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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