tDPCEBS Clock Enable B Setup before Clock B T" />
參數(shù)資料
型號(hào): LC5256MV-75FN256I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 38/99頁
文件大小: 0K
描述: IC CPLD 256MACROCELLS 256FPBGA
標(biāo)準(zhǔn)包裝: 90
系列: ispXPLD® 5000MV
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 8
宏單元數(shù): 256
輸入/輸出數(shù): 141
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
包裝: 托盤
其它名稱: 220-1724
LC5256MV-75FN256I-ND
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
39
tDPCEBS
Clock Enable B
Setup before Clock
B Time
2.33
2.33
2.33
2.33
3.03
ns
tDPCEBH
Clock Enable Hold
B after Clock B
Time
-2.95
-2.95
-2.95
-2.95
-2.27
ns
tDPADDBS
Address B Setup
before Clock B Time
-0.27
-0.27
-0.27
-0.27
-0.21
ns
tDPADDBH
Address B Hold
time after Clock B
Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tDPRWBS
R/W B Setup before
Clock B Time
-0.27
-0.27
-0.27
-0.27
-0.21
ns
tDPRWBH
R/W B Hold time
after Clock B Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tDPDATABS
Write Data B Setup
before Clock B Time
-0.27
-0.27
-0.27
-0.27
-0.21
ns
tDPDATABH
Write Data B Hold
after Clock B Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tDPRCLKAO
Read Clock A to
Output Delay
5.97
5.92
5.86
5.65
9.86
ns
tDPRCLKBO
Read Clock B to
Output Delay
5.16
5.16
5.16
5.16
6.71
ns
tDPCLKSKEW
Opposite Clock
Cycle Delay
1.40
1.40
1.40
1.40
1.83
ns
tDPRSTO
Reset to RAM
Output Delay
3.30
3.30
3.30
3.30
4.29
ns
tDPRSTR
Reset Recovery
Time
1.20
1.20
1.20
1.20
1.56
ns
tDPRSTPW
Reset Pulse Width
0.14
0.14
0.14
0.14
0.19
ns
Timing v.1.8
1. The PT-delay to clock of RAM/FIFO/CAM should be tBCLK instead of tPTCLK.
2. The PT-delay to set/reset of RAM/FIFO/CAM should be tBSR instead of tPTSR.
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
Base
Parameter
-4
-45
-5
-52
-75
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
SELECT
DEVICES
DISCONTINUED
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