參數(shù)資料
型號： LC5512MV-75Q208I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 56/99頁
文件大?。?/td> 0K
描述： IC XPLD 512MC 7.5NS 208PQFP
標準包裝： 24
系列： ispXPLD® 5000MV
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目： 16
宏單元數(shù)： 512
輸入/輸出數(shù)： 149
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 208-BFQFP
供應商設(shè)備封裝： 208-PQFP（28x28）
包裝： 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
2
Figure 1. ispXPLD 5000MX Block Diagram
Introduction
The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic
Devices (XPLDs). These devices extend the capability of Lattice’s popular SuperWIDE ispMACH 5000 architecture
by providing flexible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM
operation. Extra logic has also been included to allow efficient implementation of arithmetic functions. In addition,
sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers.
The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design
security, and extreme reconfigurability. The use of advanced process technology provides industry-leading perfor-
mance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and oper-
ating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The
ispXPLD 5000MX architecture provides predictable deterministic timing.
The availability of 3.3, 2.5 and 1.8V versions of these devices along with the flexibility of the sysIO interface helps
users meet the challenge of today’s mixed voltage designs. Inputs can be safely driven up to 5.5V when an I/O
bank is configured for 3.3V operation, making this family 5V tolerant. Boundary scan testability further eases inte-
gration into today’s complex systems. A variety of density and package options increase the likelihood of a good fit
for a particular application. Table 1 shows the members of the ispXPLD 5000MX family.
Architecture
The ispXPLD 5000MX devices consist of Multi-Function Blocks (MFBs) interconnected with a Global Routing Pool.
Signals enter and leave the device via one of four sysIO banks. Figure 1 shows the block diagram of the ispXPLD
ISP Port
Global
Routing
Pool
(GRP)
sysCLOCK
PLL 0
sysCLOCK
PLL 1
sysIO
Bank 0
MFB
VCCO3
V
CC
VREF3
VREF2
VCCO2
GCLCK3
GCLK2
RESET
GOE0
GOE1
TDO
GND
TDI
TMS
TCK
PROGRAM
OSA
sysIO
Bank 1
sysIO
Bank 3
sysIO
Bank 2
MFB
OSA
VCCO0
VCCO1
VCCP
VREF0
VREF1
GCLCK0
GNDP
GCLK1
Optional
sysCONFIG
Interface
V
CCJ
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料
PDF描述
MIC3975-1.8BMM IC REG LDO 1.8V .75A 8-MSOP
VE-BTM-CY-F2 CONVERTER MOD DC/DC 10V 50W
LC5512MV-45Q208C IC XPLD 512MC 4.5NS 208PQFP
VE-BTM-CY-F1 CONVERTER MOD DC/DC 10V 50W
VE-BT1-CY-F4 CONVERTER MOD DC/DC 12V 50W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC5512MV-75Q256C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75Q256I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75Q484C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75Q484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75Q672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*