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參數(shù)資料
| 型號： | LC5768VG-75F484I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 14/99頁 |
| 文件大小： | 0K |
| 描述： | IC XPLD 768MC 7.5NS 484FPBGA |
| 標準包裝： | 60 |
| 系列： | ispMACH™ 5000VG |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 24 |
| 宏單元數(shù)： | 768 |
| 輸入/輸出數(shù)： | 304 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BBGA |
| 供應(yīng)商設(shè)備封裝： | 484-FPBGA（23x23） |
| 包裝： | 托盤 |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
17
Output Sharing Array (OSA)
A number of I/O pads are available in each sysIO bank to route the selected number of macrocells from the MFB
outputs directly to the I/O pads in logic mode. In the ispXPLD 5000MX, the large number of inputs and PTs to the
MFB as well as the presence of the PTSA can cover most routing flexibility of signals to I/O cells. The Output Shar-
ing Array gives additional routing capability and I/O access to an MFB when a wide output function takes up the
whole MFB and cannot be easily divided across multiple MFBs. By using the OSA, the wide output function, such
as 32-bit FIFO, can have all of its output signals from the one MFB routed to I/O cells. In a given I/O block, the wide
output functions must share the I/O pads with other logic functions.
The OSA bypass option routes the MFB signal directly to the I/O cell, allowing a direct connection to the I/O cell.
The logic functions use the option to provide faster speed to the outputs. The Logic Signal Connection tables list
the OSA bypass as the primary macrocell and OSA options as alternate macrocells. Similarly, the Alternate Input
listing in the table shows the alternate macrocell input connection for a given I/O pin. Figure 17 shows the alternate
macrocell connections in an I/O cell.
sysIO Banks
The ispXPLD 5000MX devices are divided into four sysIO banks, consisting of multiple I/O cells, where each bank
is capable of supporting 16 different I/O standards. Each sysIO bank has its own I/O voltage (VCCO) and reference
voltage (VREF) resources allowing complete independence from the others.
I/O Cell
The I/O cell of the ispXPLD 5000MX devices contains an output enable (OE) MUX, a programmable tri-state output
buffer, a programmable input buffer, and programmable bus-maintenance circuitry.
The I/O cell receives inputs from its associated macrocells and the device pin. The I/O cell has a feedback line to its
associated macrocells and a direct path to GRP. The output enable (OE) MUX selects the OE signal per I/O cell.
The inputs to the OE MUX are the four global PTOE signals, PTOE and the two GOE signals. The OE MUX also
has the ability to choose either the true or inverse of each of these signals. The output of the OE MUX goes through
a logical AND with the TOE signal to allow easy tri-stating of the outputs for testing purposes. The MFBs are
grouped into segments of four for the purpose of generating Shared PTOE signals. Each Shared PTOE signal is
derived from PT 163 from one of the four MFBs. Table 10 shows the segments. The PTOE signal is derived from
the first product term in each macrocell cluster, which is directly routed to the OE MUX. Therefore, every I/O cell
can have a different OE signal. Figure 17 is a graphical representation of the I/O cell.
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