參數(shù)資料
型號: LC5768VG-75F484I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 20/99頁
文件大?。?/td> 0K
描述: IC XPLD 768MC 7.5NS 484FPBGA
標(biāo)準(zhǔn)包裝: 60
系列: ispMACH™ 5000VG
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 24
宏單元數(shù): 768
輸入/輸出數(shù): 304
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 484-BBGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
包裝: 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
23
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
IIL, IIH
1
Input or I/O Leakage
0 VIN (VCCO - 0.2V)
10
A
(VCCO - 0.2V) < VIN 3.6V
40
A
IIH
4
Input High Leakage Current
3.6V < VIN 5.5V and
3.0V VCCO 3.6V
——
3
mA
IPU
3
I/O Active Pullup Current
0 VIN 0.7 VCCO
-30
-150
A
IPD
I/O Active Pulldown Current
VIL (MAX) VIN VIH (MAX)
30
150
A
IBHLS
Bus Hold Low Sustaining Current
VIN = VIL (MAX)
30
A
IBHHS
Bus Hold High Sustaining Current VIN = 0.7 VCCO
30
A
IBHLO
Bus Hold Low Overdrive Current
0 VIN VIH (MAX)
150
A
IBHHO
Bus Hold High Overdrive Current
0 VIN VIH (MAX)
150
A
VBHT
Bus Hold Trip Points
0 VIN VIH (MAX)
VCCO * 0.35
VCCO * 0.65
A
C1
I/O Capacitance
2
VCCO = 3.3V, 2.5V, 1.8V
8
pf
VCC = 1.8V, VIO = 0 to VIH (MAX)
8
pf
C2
Clock Capacitance
2
VCCO = 3.3V, 2.5V, 1.8V
8
pf
VCC = 1.8V, VIO = 0 to VIH (MAX)
8
pf
C3
Global Input Capacitance
2
VCCO = 3.3V, 2.5V, 1.8V
8
pf
VCC = 1.8V, VIO = 0 to VIH (MAX)
8
pf
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. TA 25°C, f=1.0MHz
3. IPU on JTAG pins has a maximum of -175A for 5512MX devices.
4. 5V tolerant inputs and I/Os should be placed in banks where 3.0V VCCO 3.6V. The JTAG and sysCONFIG ports are not included for the
5V tolerant interface.
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