參數(shù)資料
型號(hào)： LC5768VG-75F484I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 7/99頁
文件大小： 0K
描述： IC XPLD 768MC 7.5NS 484FPBGA
標(biāo)準(zhǔn)包裝： 60
系列： ispMACH™ 5000VG
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目： 24
宏單元數(shù)： 768
輸入/輸出數(shù)： 304
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
包裝： 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
11
Pseudo Dual-Port SRAM Mode
In Pseudo Dual-Port SRAM Mode the multi-function array is configured as a SRAM with an independent read and
write ports that access the same 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 10 shows the block diagram of the Pseudo Dual-Port SRAM.
Write data, write address, chip select and write enable signals are always synchronous (registered). The read data
and read address signals can be synchronous or asynchronous. Reset is asynchronous. All write signals share the
same clock, and clock enable. All read signals share the same clock and clock enable. Reset is shared by both
read and write signals. Table 6 shows the possible sources for the clock, clock enable and initialization signals for
the various registers.
Figure 10. Pseudo Dual-Port SRAM Block Diagram
Table 6. Register Clock, Clock Enable, and Reset in Pseudo Dual-Port SRAM Mode
Register
Input
Source
Write Address, Write
Data, Write Enable,
and Write Chip Select
Clock
WCLK or one of the global clocks (CLK0 - CLK3). The selected signal can
be inverted if desired.
Clock Enable
WCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Reset
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
Read Data and Read
Address
Clock
RCLK or one of the global clocks (CLK0 - CLK3). The selected signal can be
inverted if desired.
Clock Enable
RCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Reset
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
‘
68 Inputs
From
Routing
16,384 bit
Pseudo
Dual
Port
SRAM
Array
Write Address
(WAD[0:8-13])
Write Clk Enable (WCEN)
Write Clock (WCLK)
Read Address
(RAD[0:8-13])
Write Enable (WE)
Write Chip Sel (WCS[0,1])
Reset (RST)
Read Clk Enable (RCEN)
Read Clock (RCLK)
Write Data
(WD[0:0,1,3,7,15,31])
RESET
CLK0
CLK3
CLK1
CLK2
Read Data
(RD[0:0-15])
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料
PDF描述
RCM10DRSH-S288 CONN EDGECARD 20POS .156 EXTEND
TAJS334K050RNJ CAP TANT 0.33UF 50V 10% 1206
LC5768VG-5F484C IC XPLD 768MC 5NS 484FPBGA
VI-2TV-CY-F3 CONVERTER MOD DC/DC 5.8V 50W
VI-2TV-CY-F1 CONVERTER MOD DC/DC 5.8V 50W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC5768VG-75FN484I 制造商:Lattice Semiconductor Corporation 功能描述:
LC58 制造商:Microsemi Corporation 功能描述:TVS SGL UNI-DIR 58V 1.5KW 2PIN DO-13 - Bulk 制造商:Microsemi Corporation 功能描述:TVS 1500V LOW CAP DO-202AA 制造商:Microsemi Corporation 功能描述:TVS DIODE 58VWM 103VC DO202AA
LC5800 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
LC5805 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:SINGLE-CHIP 4-BIT MICROCOMPUTER WITH LCD DRIVERS
LC580Z 制造商:SEOUL 制造商全稱:Seoul Semiconductor 功能描述:GREEN OVAL LAMP LED
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*