參數(shù)資料
型號(hào): LFX200B-03FN256C
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 35/119頁(yè)
文件大小: 0K
描述: IC FPGA 200K GATES 256-BGA
標(biāo)準(zhǔn)包裝: 90
系列: ispXPGA®
邏輯元件/單元數(shù): 2704
RAM 位總計(jì): 113664
輸入/輸出數(shù): 160
門數(shù): 210000
電源電壓: 2.3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
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Lattice Semiconductor
ispXPGA Family Data Sheet
18
High Speed Serial Interface Block (sysHSI Block)
1
The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The
ispXPGA devices have multiple sysHSI blocks.
Each sysHSI block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and
Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDES can be used as a full
duplex channel. The two SERDES in sysHSI blocks share a common clock and must operate at the same nominal
frequency. Figure 20 shows the sysHSI block.
Device features support two data coding modes: 10B/12B and 8B/10B (for use with other encoding schemes, see
Lattice’s sysHSI technical notes). The encoding and decoding of the 10B/12B standard are performed within the
sysHSI block. For the 8B/10B standard, the symbol boundaries are aligned internally but the encoding and decod-
ing are performed outside the sysHSI block.
Each SERDES block receives a single high speed serial data input stream (with embedded clock) from an input,
and provide a low speed 10-bit wide data stream and a recovered clock to the device. For transmitting, SERDES
converts a 10-bit wide low-speed data stream to a single high-speed data stream with embedded clock for output.
Additionally, multiple sysHSI blocks can be grouped together to form a source synchronous interface of 1-10 chan-
nels.
For more information on the SERDES/CDR, refer to TN1020, sysHSI Usage Guidelines.
Figure 20. sysHSI Block Diagram
1.
“E-Series” does not support sysHSI.
Shared
Source
Synchronous
Pins
Dr
iv
e
Multiple
sysHSI
b
loc
ks
REFCLK
SOUT
SIN
SS_CLKOUT
SS_CLKIN
SERDES(HSI#A)
CAL
CSLOCK
SERDES(HSI#B)
SOUT
SIN
TXD
RXD
RECCLK
SYDT
10
TXD
RXD
RECCLK
SYDT
10
To PICs
From PICs
From Global
Clock Tree
sysIO
From PICs
To PICs
CDRRST
From PICs
CDRRST
From PICs
Deserializer and Clock/Data Recovery
CSPLL
Serializer
Deserializer and Clock/Data Recovery
SELECT
DEVICES
DISCONTINUED
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