參數(shù)資料
型號: LFX200B-03FN256C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 72/119頁
文件大小: 0K
描述: IC FPGA 200K GATES 256-BGA
標準包裝: 90
系列: ispXPGA®
邏輯元件/單元數(shù): 2704
RAM 位總計: 113664
輸入/輸出數(shù): 160
門數(shù): 210000
電源電壓: 2.3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BGA
供應商設備封裝: 256-FPBGA(17x17)
Lattice Semiconductor
ispXPGA Family Data Sheet
52
sysHSI Block AC Specifications
Operating Frequency Ranges
LOCKIN Time
Symbol
Description
Mode
Test
Condition
Device
-5
1
-4
-3
Units
Min.
Max.
Min.
Max.
Min.
Max.
fCLK
Reference Clock
Frequency
SS:CAL
LFX125B/C
50
200
50
200
50
200
MHz
LFX200B/C
50
188
50
188
50
188
LFX500B/C
50
188
50
188
50
188
LFX1200B/C
50
175
50
175
50
175
10B12B
LFX125B/C
33673367
33
67
MHz
LFX200B/C
33633363
33
63
LFX500B/C
33633363
33
63
LFX1200B/C
33
58
33
58
33
58
8B10B
LFX125B/C
40
80
40
80
40
80
MHz
LFX200B/C
40754075
40
75
LFX500B/C
40754075
40
75
LFX1200B/C
40
70
40
70
40
70
fSIN
2
Serial Input
SS:CAL
with eoSIN
LFX125B/C
400
800
400
800
400
800
Mbps
LFX200B/C
400
750
400
750
400
750
LFX500B/C
400
750
400
750
400
750
LFX1200B/C
400
700
400
700
400
700
10B12B
with eoSIN
LFX125B/C
400
800
400
800
400
800
Mbps
LFX200B/C
400
750
400
750
400
750
LFX500B/C
400
750
400
750
400
750
LFX1200B/C
400
700
400
700
400
700
8B10B
with eoSIN
LFX125B/C
400
800
400
800
400
800
Mbps
LFX200B/C
400
750
400
750
400
750
LFX500B/C
400
750
400
750
400
750
LFX1200B/C
400
700
400
700
400
700
fOUT
2
Serial Out
LVDS
CL = 5 pF,
RL = 100
fCLK with no jit-
ter
LFX125B/C
400
800
400
800
400
800
Mbps
LFX200B/C
400
750
400
750
400
750
LFX500B/C
400
750
400
750
400
750
LFX1200B/C
400
700
400
700
400
700
1. Only available for ispXPGA 125B, 200B, 500B and 1200B (2.5V/3.3V) devices.
2. fSIN and fSOUT speeds are supported at VCC and VCCP at 1.7V to 1.9V for ispXPGA 1.8V devices.
Symbol
Description
Mode
Condition
Min
Max
Unit
tSCLOCK
CSPLL Lock Time
All
After input is stabilized
25
S
tCDRLOCK
CDRPLL Lock-in Time
SS
With SS mode sync pattern
1024
tRCP
1
10B12B
With 10B12B sync pattern
1024
tRCP
8B10B
With 8B10B idle pattern
960
tRCP
tSYNC
SyncPat Length
SS
1200
tRCP
tCAL
CAL Duration
SS
1100
tRCP
tSUSYNC
SyncPat Set-up Time to CAL
SS
50
tRCP
tHDSYNC
SyncPat Hold Time from CAL
SS
50
tRCP
1. REFCLK clock period.
SELECT
DEVICES
DISCONTINUED
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