參數(shù)資料
型號: LFX200B-03FN256C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 78/119頁
文件大?。?/td> 0K
描述: IC FPGA 200K GATES 256-BGA
標準包裝: 90
系列: ispXPGA®
邏輯元件/單元數(shù): 2704
RAM 位總計: 113664
輸入/輸出數(shù): 160
門數(shù): 210000
電源電壓: 2.3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BGA
供應商設備封裝: 256-FPBGA(17x17)
Lattice Semiconductor
ispXPGA Family Data Sheet
57
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Units
tPWH
Input clock, high time
80% to 80%
1.2
ns
tPWL
Input clock, low time
20% to 20%
1.2
ns
tR, tF
Input Clock, rise and fall time
20% to 80%
3.0
ns
tINSTB
Input clock stability, cycle to cycle (peak)
+/- 250
ps
fMDIVIN
M Divider input, frequency range
10
320
MHz
fMDIVOUT
M Divider output, frequency range
10
320
MHz
fNDIVIN
N Divider input, frequency range
10
320
MHz
fNDIVOUT
N Divider output, frequency range
10
320
MHz
fVDIVIN
V Divider input, frequency range
100
400
MHz
fVDIVOUT
V Divider output, frequency range
10
320
MHz
tOUTDUTY
output clock, duty cycle
40
60
%
tJIT(CC)
Output clock, cycle to cycle jitter (peak)
Clean reference
1
10MHz fMDIVOUT 40MHz or
100MHz f VDIVIN 160MHz
—+/- 600
ps
Clean reference
1
40MHz fMDIVOUT 320MHz and
160MHz fVDIVIN 400MHz
—+/- 150
ps
tJIT(PER)
2
Output clock, period jitter (peak)
Clean reference
1
10MHz fMDIVOUT 40MHz or
100MHz fVDIVIN 160MHz
—+/- 600
ps
Clean reference
1
40MHz fMDIVOUT 320MHz and
160MHz fVDIVIN 400MHz
—+/- 150
ps
tCLK_OUT_DELAY Input clock to CLK_OUT delay
Internal feedback
3.0
ns
tPHASE
Input clock to external feedback delta
External feedback
1.5
ns
tLOCK
Time to acquire phase lock after input stable
25
us
tPLL_DELAY
Delay increment (Lead/Lag)
Typical = +/- 250ps
+/- 120 +/- 550
ps
tRANGE
Total output delay range (lead/lag)
+/- 0.84 +/- 3.85
ns
tPLL_RSTW
Minimum reset pulse width
1.8
ns
tCLK_IN
3
Global clock input delay
1.0
ns
tPLL_SEC_DELAY Secondary PLL output delay
1.5
ns
1. This condition assures that the output phase jitter will remain within specifications. Jitter spec is based on optimized M, N and V settings
determined by the ispLEVER software.
2. Accumulated jitter measured over 10,000 waveform samples
3. Internal timing for reference only.
SELECT
DEVICES
DISCONTINUED
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LFX200B-03FN516C 功能描述:FPGA - 現(xiàn)場可編程門陣列 210K Gt ispJTAG 2.5 /3.3V -3 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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