參數(shù)資料
型號(hào): LH52D1000
廠商: Sharp Corporation
英文描述: CMOS 1M (128K x 8) Static Ram
中文描述: 100萬的CMOS(128K的× 8)靜態(tài)RAM
文件頁數(shù): 4/12頁
文件大?。?/td> 81K
代理商: LH52D1000
AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
PARAMETER
MODE
NOTE
Input pulse level
Input rise and fall time
Input and output timing Ref. level
Output load
0.4 V to 2.4 V
5 ns
1.5 V
100 pF + 1TTL
1
NOTE:
1.
Including scope and jig capacitance.
READ CYCLE (T
A
= -40
°
C to +85
°
C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
Address access time
CE
1
access time
CE
2
access time
Output enable to output valid
Output hold from address change
CE
1
Low to output active
CE
2
High to output active
OE Low to output active
CE
1
High to output in High impedance
CE
2
Low to output in High impedance
OE High to output in High impedance
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OH
t
LZ1
t
LZ2
t
OLZ
t
HZ1
t
HZ2
t
OHZ
85
10
5
5
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
85
85
85
45
35
35
35
NOTE:
1.
Active output to High impedance and High impedance to output active tests specified for a
±
200 mV transition
from steady state levels into the test load.
WRITE CYCLE (T
A
= -40
°
C to +85
°
C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Write cycle time
CE
1
Low to end of write
CE
2
High to end of write
Address setup time
Write pulse width
Write recovery time
Input data setup time
Input data hold time
WE High to output active
WE Low to output in High impedance
OE High to output in High impedance
t
WC
t
CW1
t
CW2
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
t
WZ
t
OHZ
85
75
75
0
60
0
35
0
0
0
0
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
NOTE:
1.
Active output to High impedance and High impedance to output active tests specified for a
±
200 mV transition
from steady state levels into the test load.
LH52D1000
CMOS 1M (128K
×
8) Static RAM
4
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