參數(shù)資料
型號(hào)： LH7A400N0E000
廠商： Sharp Corporation
英文描述： 32-Bit System-on-Chip
中文描述： 32位系統(tǒng)級(jí)芯片
文件頁(yè)數(shù)： 25/53頁(yè)
文件大?。?/td> 446K
代理商： LH7A400N0E000
32-Bit System-on-Chip
LH7A400
Preliminary Data Sheet
12/8/03
25
SYSTEM DESCRIPTIONS
ARM922T Processor
The LH7A400 microcontroller features the
ARM922T cached core with an Advanced High Perfor-
mance Bus (AHB) interface. The processor is a mem-
ber of the ARM9T family of processors. For more
information, see the ARM document, ‘ARM922T Tech-
nical Reference Manual’, available on ARM’s website
at www.arm.com.
Clock and State Controller
The clocking scheme in the LH7A400 is based
around two primary oscillator inputs. These are the
14.7456 MHz input crystal and the 32.768 kHz real time
clock oscillator. See Figure 3. The 14.7456 MHz oscil-
lator is used to generate the main system clock
domains for the LH7A400, where as the 32.768 kHz is
used for controlling the power down operations and
real time clock peripheral. The clock and state control-
ler provides the clock gating and frequency division
necessary, and then supplies the clocks to the proces-
sor and to the rest of the system. The amount of clock
gating that actually takes place is dependent on the
current power saving mode selected.
The 32.768 kHz clock provides the source for the
Real Time Clock tree and power-down logic.This clock
is used for the power state control in the design and is
the only clock in the LH7A400 that runs permanently.
The 32.768 kHz clock is divided down to 1 Hz using a
ripple divider to save power. This generated 1 Hz clock
is used in the Real Time Clock counter.
The 14.7456 MHz source is used to generate the
main system clocks for the LH7A400. It is the source
for PLL1 and PLL2, it acts as the primary clock to the
peripherals and is the source clock to the Programma-
ble clock (PGM) divider.
PLL1 provides the main clock tree for the chip, it
generates the following clocks: FCLK, HCLK and
PCLK. FCLK is the clock that drives the ARM922T
core. HCLK is the main bus (AHB) clock, as such it
clocks all memory interfaces, bus arbitrators and the
AHB peripherals. HCLK is generated by dividing FCLK
by 1, 2, 3, or 4. HCLK can be gated by the system to
enable low power operation. PCLK is the peripheral
bus (APB) clock. It is generated by dividing HCLK by
either 2, 4, or 8.
PLL2 is used to generate a fixed frequency of
48 MHz for the USB peripheral.
Figure 2. Application Diagram
CODEC
BATTERY
DC to DC
VOLTAGE
GENERATION
CIRCUITRY
MULTIMEDIA
CARD
TOUCH
SCREEN
CONTR.
MMC
SCI
PCMCIA
COMPACT
FLASH
UART
USB
SDRAM
SRAM
ROM
FLASH
DMA
AC97
STN/TFT/
AD-TFT
IR
GPIO
SSP
UART
LH7A400
PC
CARD
LH7A400-3
1
2
3
4
5
6
7
8
9
*
0
#
BMI
SMART
CARD
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參數(shù)描述
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LH7A400N0E000B5,551 制造商:NXP Semiconductors 功能描述:
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LH7A400N0F000B3A,551 制造商:NXP Semiconductors 功能描述:
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