參數(shù)資料
型號: LH7A400N0E000
廠商: Sharp Corporation
英文描述: 32-Bit System-on-Chip
中文描述: 32位系統(tǒng)級芯片
文件頁數(shù): 7/53頁
文件大?。?/td> 446K
代理商: LH7A400N0E000
32-Bit System-on-Chip
LH7A400
Preliminary Data Sheet
12/8/03
7
F9
A9
B9
D9
E9
C11
C9
A9
B9
A8
nRAS
DQM0
DQM1
DQM2
DQM3
Synchronous Memory Row Address Strobe Signal HIGH
Synchronous Memory Data Mask 0
Synchronous Memory Data Mask 1
Synchronous Memory Data Mask 2
Synchronous Memory Data Mask 3
GPIO Port A
LCD Data bit 16. This CLCDC output signal is
always LOW.
GPIO Port A
LCD Data bit 17. This CLCDC output signal is
always LOW.
HIGH
HIGH
HIGH
HIGH
HIGH
12 mA
12 mA
12 mA
12 mA
12 mA
HIGH
HIGH
HIGH
HIGH
J5
K1
PA0/LCDVD16
Input: PA0
No Change
8 mA
K1
K2
PA1/LCDVD17
Input: PA1
No Change
8 mA
K2
K3
K5
L1
L2
L3
K3
K4
K6
K5
L1
L2
PA2
PA3
PA4
PA5
PA6
PA7
GPIO Port A
Input
No Change
8 mA
L4
L3
PB0/UARTRX1
GPIO Port B
UART1 Receive Data Input
Input: PB0
No Change
8 mA
L5
M1
PB1/UARTTX3
GPIO Port B
UART3 Transmit Data Out
Input: PB1
LOW if
UART3 is
Enabled,
otherwise
No Change
8 mA
L7
M2
PB2/UARTRX3
GPIO Port B
UART3 Receive Data In
GPIO Port B
UART3 Clear to Send
GPIO Port B
UART3 Data Carrier Detect
GPIO Port B
UART3 Data Set Ready
Input: PB2
No Change
8 mA
M2
M3
PB3/
UARTCTS3
PB4/
UARTDCD3
PB5/
UARTDSR3
Input: PB3
No Change
8 mA
M4
L5
Input: PB4
No Change
8 mA
N1
N1
Input: PB5
No Change
8 mA
N2
N2
PB6/SWID/
SMBD
GPIO Port B
Single Wire Data
Smart Battery Data
Input: PB6
Input if SMB
is Enabled,
otherwise
No Change
Input if SMB
is Enabled,
otherwise
No Change
8 mA
N3
M4
PB7/SMBCLK
GPIO Port B
Smart Battery Clock
Input: PB7
8 mA
P1
P1
PC0/UARTTX1
GPIO Port C
UART1 Transmit Data Output
GPIO Port C
HR-TFT Power Save
GPIO Port C
HR-TFT Power Sequence Control
GPIO Port C
HR-TFT Gray Scale Voltage Reverse
GPIO Port C
HR-TFT Reset Row Driver Counter
GPIO Port C
HR-TFT Row Driver Clock
LOW: PC0
No Change
12 mA
P2
P2
PC1/LCDPS
LOW: PC1
No Change
12 mA
R1
R1
PC2/
LCDVDDEN
LOW: PC2
No Change
12 mA
K6
M5
PC3/LCDREV
LOW: PC3
No Change
12 mA
L8
P3
PC4/LCDSPS
LOW: PC4
No Change
12 mA
T1
N4
PC5/LCDCLS
LOW: PC5
No Change
12 mA
Table 1. Functional Pin List (Cont’d)
PBGA
PIN
CABGA
PIN
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
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