32-Bit System-on-Chip
LH7A400
Preliminary Data Sheet
12/8/03
9
L6
P4
PG2/nPCIOR
GPIO Port G
I/O Read Strobe for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
GPIO Port G
I/O Write Strobe for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
GPIO Port G
Register Memory Access for PC Card (PCMCIA
or CompactFlash) in single or dual card mode
GPIO Port G
Card Enable 1 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode.
This signal and nPCCE2 are used by the PC
Card for decoding low and high byte accesses.
GPIO Port G
Card Enable 2 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode.
This signal and nPCCE1 are used by the PC
Card for decoding low and high byte accesses.
GPIO Port G
Direction for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
GPIO Port H
Reset Card 1 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
GPIO Port H
Address Bit 8 for PC Card (CompactFlash) in
single card mode
Reset Card 2 for PC Card (PCMCIA or
CompactFlash) in dual card mode
GPIO Port H
Enable Card 1 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode.
This signal is used for gating other control sig-
nals to the appropriate PC Card.
GPIO Port H
Address Bit 9 for PC Card (CompactFlash) in
single card mode
Address Bit 25 for PC Card (PCMCIA) in single
card mode
Enable Card 2 for PC Card (PCMCIA or
CompactFlash) in dual card mode. This signal
is used for gating other control signals to the
appropriate PC Card.
GPIO Port H
WAIT Signal for Card 1 for PC Card (PCMCIA
or CompactFlash) in single or dual card mode
GPIO Port H
Address Bit 10 for PC Card (CompactFlash) in
single card mode
Address Bit 24 for PC Card (PCMCIA) in single
card mode
WAIT Signal for Card 2 for PC Card (PCMCIA
or CompactFlash) in dual card mode
LOW: PG2
No Change
8 mA
M6
R3
PG3/nPCIOW
LOW: PG3
No Change
8 mA
N6
T2
PG4/nPCREG
LOW: PG4
No Change
8 mA
M7
P5
PG5/nPCCE1
LOW: PG5
No Change
8 mA
M8
R4
PG6/nPCCE2
LOW: PG6
No Change
8 mA
N4
T3
PG7/PCDIR
LOW: PG7
No Change
8 mA
P4
P6
PH0/
PCRESET1
Input: PH0
No Change
8 mA
R4
T4
PH1/CFA8/
PCRESET2
Input: PH1
No Change
8 mA
T4
M7
PH2/
nPCSLOTE1
Input: PH2
No Change
8 mA
N7
T5
PH3/CFA9/
PCMCIAA25/
nPCSLOTE2
Input: PH3
No Change
8 mA
P8
R6
PH4/
nPCWAIT1
Input: PH4
No Change
8 mA
P5
R7
PH5/CFA10/
PCMCIAA24/
nPCWAIT2
Input: PH5
No Change
8 mA
Table 1. Functional Pin List (Cont’d)
PBGA
PIN
CABGA
PIN
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE