參數(shù)資料
型號(hào)： LH7A400N0E000
廠商： Sharp Corporation
英文描述： 32-Bit System-on-Chip
中文描述： 32位系統(tǒng)級(jí)芯片
文件頁(yè)數(shù)： 37/53頁(yè)
文件大?。?/td> 446K
代理商： LH7A400N0E000
32-Bit System-on-Chip
LH7A400
Preliminary Data Sheet
12/8/03
37
AC Specifications
All signals described in Table 9 relate to transi-
tions after a reference clock signal. The illustration in
Figure 6 represents all cases of these sets of mea-
surement parameters.
The reference clock signals in this design are:
HCLK, internal System Bus clock (‘C’ in timing data)
PCLK, Peripheral Bus clock
SSPCLK, Synchronous Serial Port clock
UARTCLK, UART Interface clock
LCDDCLK, LCD Data clock from the
LCD Controller
ACBITCLK, AC97 clock
SCLK, Synchronous Memory clock.
All signal transitions are measured from the 50%
point of the clock to the 50% point of the signal.
For outputs from the LH7A400, tOVXXX (e.g. tOVA)
represents the amount of time for the output to become
valid from a valid address bus, or rising edge of the
peripheral clock. Maximum requirements for tOVXXX
are shown in Table 9.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid from the valid
address bus, or rising edge of the peripheral clock. Min-
imum requirements for tOHXXX are listed in Table 9.
For Inputs, tISXXX (e.g. tISD) represents the amount
of time the input signal must be valid after a valid
address bus, or rising edge of the peripheral clock. Max-
imum requirements for tISXXX are shown in Table 9.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the output must be held valid from the
valid address bus, or rising edge of the peripheral
clock. Minimum requirements are shown in Table 9.
Figure 6. LH7A400 Signal Timing
REFERENCE
CLOCK
OUTPUT
SIGNAL (O)
INPUT
SIGNAL (I)
tOVXXX
tOHXXX
tISXXX tIHXXX
7A400-28
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