32-Bit System-on-Chip
LH7A400
Preliminary Data Sheet
12/8/03
31
Direct Memory Access Controller (DMA)
The DMA Controller interfaces streams from the fol-
lowing three peripherals to the system memory:
USB (1 Tx and 1 Rx DMA Channel)
MMC (1 Tx and 1 Rx DMA Channel)
AC97 (3 Tx and 3 Rx DMA Channels).
Each has its own bi-directional peripheral DMA bus
capable of transferring data in both directions simulta-
neously. All memory transfers take place via the main
system AHB bus.
DMA Specific features are:
Independent DMA channels for Tx and Rx
Two Buffer Descriptors per channel to avoid poten-
tial data under/over-flows due to software introduced
latency
No Buffer wrapping
Buffer size may be equal to, greater than or less than
the packet size. Transfers can automatically switch
between buffers.
Maskable interrupt generation
Internal arbitration between DMA Channels and
external bus arbiter.
For DMA Data transfer sizes, byte, word and quad-
word data transfers are supported.
A set of control and status registers are available to
the system processor for setting up DMA operations
and monitoring their status. A system interrupt is gen-
erated when any or all of the DMA channels wish to
inform the processor that a new buffer needs to be allo-
cated. The DMA controller services three peripherals
using ten DMA channels, each with its own peripheral
DMA bus capable of transferring data in both directions
simultaneously.
The MMC and USB peripherals each use two DMA
channels, one for transmit and one for receive. The
AC97 peripheral uses six DMA channels (three trans-
mit and three receive) to allow different sample fre-
quency data queues to be handled with low software
overheads. The DMA Controller does not support
memory to memory transfers.
USB Device
The features of the USB are:
Fully compliant to USB 1.1 specification
Provides a high level interface that shields the firm-
ware from USB protocol details
Compatible with both OpenHCI and Intel’s UHCI
standards
Supports full-speed (12 Mbps) functions
Supports Suspend and Resume signalling.
Color LCD Controller
The LH7A400’s LCD Controller is programmable to
support up to 1,024 × 768, 16-bit color LCD panels. It
interfaces directly to STN, color STN, TFT, AD-TFT,
and HR-TFT panels. Unlike other LCD controllers, the
LH7A400’s LCD Controller incorporates the timing con-
version logic from TFT to HR-TFT, allowing a direct
interface to HR-TFT and minimizing external chip count.
The Color LCD Controller features support for:
Up to 1,024 × 768 Resolution
16-bit Video Bus
STN, Color STN, AD-TFT, HR-TFT, TFT panels
Single and Dual Scan STN panels
Up to 15 Gray Shades
Up to 64,000 Colors
AC97 Advanced Audio Codec Interface
The AC97 Advanced Audio Codec controller
includes a 5-pin serial interface to an external audio
codec. The AC97 LINK is a bi-directional, fixed rate,
serial Pulse Code Modulation (PCM) digital stream,
dividing each audio frame into 12 outgoing and 12
incoming data streams (slots), each with 20-bit sample
resolution.
The AC97 controller contains logic that controls the
AC97 link to the Audio Codec and an interface to the
AMBA APB.
Its main features include:
Serial-to-parallel conversion for data received from
the external codec
Parallel-to-serial conversion for data transmitted to
the external codec
Reception/Transmission of control and status infor-
mation via the AMBA APB interface
Supports up to 4 different codec sampling rates at a
time with its 4 transmit and 4 receive channels. The
transmit and receive paths are buffered with internal
FIFO memories, allowing data to be stored indepen-
dently in both transmit and receive modes. The out-
going data for the FIFOs can be written via either the
APB interface or with DMA channels 1 - 3.