- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358799 > LH7A400N0W000 (Sharp Corporation) 32-Bit System-on-Chip PDF資料下載
參數(shù)資料
| 型號： | LH7A400N0W000 |
| 廠商： | Sharp Corporation |
| 英文描述： | 32-Bit System-on-Chip |
| 中文描述： | 32位系統(tǒng)級芯片 |
| 文件頁數(shù)： | 32/53頁 |
| 文件大?。?/td> | 446K |
| 代理商： | LH7A400N0W000 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
LH7A400
32-Bit System-on-Chip
32
12/8/03
Preliminary Data Sheet
Audio Codec Interface (ACI)
The ACI provides:
A digital serial interface to an off-chip 8-bit CODEC
All the necessary clocks and timing pulses to per-
form serialization or de-serialization of the data
stream to or from the CODEC device.
The interface supports full duplex operation and the
transmit and receive paths are buffered with internal
FIFO memories allowing up to 16 bytes to be stored
independently in both transmit and receive modes.
The ACI includes a programmable frequency divider
that generates a common transmit and receive bit clock
output from the on-chip ACI clock input (ACICLK).
Transmit data values are output synchronous with the
rising edge of the bit clock output. Receive data values
are sampled on the falling edge of the bit clock output.
The start of a data frame is indicated by a synchroniza-
tion output signal that is synchronous with the bit clock.
Synchronous Serial Port (SSP)
The LH7A400 SSP is a master-only interface for
synchronous serial communication with device periph-
eral devices that has either Motorola SPI, National
Semiconductor MICROWIRE or Texas Instruments
Synchronous Serial Interfaces.
The LH7A400 SSP performs serial-to-parallel con-
version on data received from a peripheral device. The
transmit and receive paths are buffered with internal
FIFO memories allowing up to eight 16-bit values to be
stored independently in both transmit and receive
modes. Serial data is transmitted on SSPTXD and
received on SSPRXD.
The LH7A400 SSP includes a programmable bit rate
clock divider and prescaler to generate the serial output
clock SCLK from the input clock SSPCLK. Bit rates are
supported to 2 MHz and beyond, subject to choice of
frequency for SSPCLK; the maximum bit rate will usu-
ally be determined by peripheral devices.
UART/IrDA
The LH7A400 contains three UARTs, UART1,
UART2, and UART3.
The UART performs:
Serial-to-Parallel conversion on data received from
the peripheral device
Parallel-to-Serial conversion on data transmitted to
the peripheral device.
The transmit and receive paths are buffered with inter-
nal FIFO memories allowing up to 16 bytes to be stored
independently in both transmit and receive modes.
The UART can generate:
Four individually maskable interrupts from the
receive, transmit and modem status logic blocks
A single combined interrupt so that the output is
asserted if any of the individual interrupts are
asserted and unmasked.
If a framing, parity or break error occurs during
reception, the appropriate error bit is set, and is stored
in the FIFO. If an overrun condition occurs, the overrun
register bit is set immediately and the FIFO data is pre-
vented from being overwritten. UART1 also supports
IrDA 1.0 (15.2 kbit/s).
The modem status input signals Clear to Send
(CTS), Data Carrier Detect (DCD) and Data Set Ready
(DSR) are supported on UART2 and UART3.
Timers
Two identical timers are integrated in the LH7A400.
Each of these timers has an associated 16-bit read/write
data register and a control register. Each timer is loaded
with the value written to the data register immediately,
this value will then be decremented on the next active
clock edge to arrive after the write. When the timer
underflows, it will immediately assert its appropriate
interrupt. The timers can be read at any time. The clock
source and mode is selectable by writing to various bits
in the system control register. Clock sources are
508 kHz and 2 kHz.
Timer 3 (TC3) has the same basic operation, but is
clocked from a single 7.3728 MHz source. It has the
same register arrangement as Timer 1 and Timer 2, pro-
viding a load, value, control and clear register. Once the
timer has been enabled and is written to, unlike the
Timer 1 and Timer 2, will decrement the timer on the
next rising edge of the 7.3728 MHz clock after the data
register has been updated. All the timers can operate in
two modes, free running mode or pre-scale mode.
FREE-RUNNING MODE
In free-running mode, the timer will wrap around to
0xFFFF when it underflows and continue counting down.
PRE-SCALE MODE
In pre-scale (periodic) mode, the value written to
each timer is automatically re-loaded when the timer
underflows. This mode can be used to produce a pro-
grammable frequency to drive the buzzer or generate a
periodic interrupt.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH7A404 | 32 BIT SYSTEM ON CHIP |
| LHA674 | SIDELED Super-Bright, Hyper-Red GaAIAs-LED |
| LHA674-KM | SIDELED Super-Bright, Hyper-Red GaAIAs-LED |
| LHA674-L | SIDELED Super-Bright, Hyper-Red GaAIAs-LED |
| LHA674-LN | SIDELED Super-Bright, Hyper-Red GaAIAs-LED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH7A404 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:32 BIT SYSTEM ON CHIP |
| LH7A404N0E000B0A | 功能描述:IC ARM922T MCU 200MHZ 324CABGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:BlueStreak ; LH7A 標(biāo)準(zhǔn)包裝:96 系列:PIC® 16F 核心處理器:PIC 芯體尺寸:8-位 速度:20MHz 連通性:I²C，SPI 外圍設(shè)備:欠壓檢測/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):11 程序存儲器容量:3.5KB（2K x 14） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:128 x 8 電壓 - 電源 (Vcc/Vdd):2.3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 包裝:管件 |
| LH7A404N0E000B0A,551 | 制造商:NXP Semiconductors 功能描述: |
| LH7A404N0E000B1A,551 | 制造商:NXP Semiconductors 功能描述: |
| LH7A404N0E000B2,551 | 制造商:NXP Semiconductors 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。