參數(shù)資料
型號(hào)： LH7A400N0W000
廠(chǎng)商： Sharp Corporation
英文描述： 32-Bit System-on-Chip
中文描述： 32位系統(tǒng)級(jí)芯片
文件頁(yè)數(shù)： 8/53頁(yè)
文件大小： 446K
代理商： LH7A400N0W000
LH7A400
32-Bit System-on-Chip
8
12/8/03
Preliminary Data Sheet
T2
R2
PC6/LCDHRLP
GPIO Port C
LCD Latch Pulse
GPIO Port C
LCD Start Pulse Left
LOW: PC6
No Change
12 mA
R2
N5
PC7/LCDSPL
LOW: PC7
No Change
12 mA
M11
L11
K8
N11
R9
T9
P10
R10
L10
N10
M9
M9
K10
P10
T11
T12
R11
R12
T13
T9
K9
T10
PD0/LCDVD8
PD1/LCDVD9
PD2/LCDVD10
PD3/LCDVD11
PD4/LCDVD12
PD5/LCDVD13
PD6/LCDVD14
PD7/LCDVD15
PE0/LCDVD4
PE1/LCDVD5
PE2/LCDVD6
GPIO Port D
LCD Video Data Bus
LOW: PD0
LOW: PD1
LOW: PD2
LOW: PD3
LOW: PD4
LOW: PD5
LOW: PD6
LOW: PD7
Input: PE0
Input: PE1
Input: PE2
LOW if
Dual-Panel
LCD is
Enabled;
otherwise,
No Change
12 mA
GPIO Port E
LCD Video Data Bus
LOW if 8-bit
LCD is
Enabled,
otherwise
No Change
12 mA
M10
R10
PE3/LCDVD7
Input: PE3
A6
A5
PF0/INT0
GPIO Port F
External FIQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
Input: PF0
(Schmitt)
No Change
8 mA
B6
B4
PF1/INT1
GPIO Port F
External IRQ Interrupts. Interrupts can be level
or edge triggered and are internally debounced.
Input: PF1
(Schmitt)
Input: PF2
(Schmitt)
No Change
8 mA
C6
E7
PF2/INT2
No Change
8 mA
H8
B3
PF3/INT3
GPIO Port F
External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
GPIO Port F
External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
Smart Card Supply Voltage Enable
GPIO Port F
External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
Smart Card Detection
GPIO Port F
External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
Ready for Card 1 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
GPIO Port F
External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
Ready for Card 2 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
GPIO Port G
Output Enable for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
GPIO Port G
Write Enable for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
Input: PF3
(Schmitt)
No Change
8 mA
B5
C5
PF4/INT4/
SCVCCEN
Input: PF4
(Schmitt)
LOW if SCI
is Enabled;
otherwise,
No Change
8 mA
D6
D6
PF5/INT5/
SCDETECT
Input: PF5
(Schmitt)
No Change
8 mA
E6
A4
PF6/INT6/
PCRDY1
Input: PF6
(Schmitt)
No Change
8 mA
C5
A3
PF7/INT7/
PCRDY2
Input: PF7
(Schmitt)
No Change
8 mA
R3
M6
PG0/nPCOE
LOW: PG0
No Change
8 mA
T3
T1
PG1/nPCWE
LOW: PG1
No Change
8 mA
Table 1. Functional Pin List (Cont’d)
PBGA
PIN
CABGA
PIN
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
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