參數(shù)資料
型號: LM4931
廠商: National Semiconductor Corporation
英文描述: Audio Subsystem with Mono High Efficiency Loudspeaker and Stereo Headphone Amplifiers
中文描述: 與單聲道音頻子系統(tǒng)高效揚聲器和立體聲耳機放大器
文件頁數(shù): 14/47頁
文件大?。?/td> 1640K
代理商: LM4931
Basic Configuration Register
This register used to configure the basic function of the chip.
DEFAULT CHART FOR BASIC_CONFIG (00h)
DATA BIT
DEFAULT
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
BASIC_CONFIG (00h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
3:0
Register
MODE
Description
The LM4931 can be placed in one of several modes that dictate the basic operation.
When a new mode is selected the LM4931 will change operation silently and will
reconfigure the power management profile automatically. The modes are described as
follows: (Note 13)
3:0
Mono Speaker
Amplifier
Source
0000
None
None
Headphone
Left Source
Headphone
Right Source
Comment
None
Powerdown
mode
Standby mode
Mono speaker
mode
Headphone call
mode
Conference call
mode
L+R mixed to
mono speaker
Headphone
stereo audio
L+R mixed to
mono speaker +
stereo
headphone
audio
Mixed mode
Mixed mode
0001
0010
None
Voice
None
None
None
None
0011
None
Voice
Voice
0100
Voice
Voice
Voice
0101
Audio (L+R)
None
None
0110
None
Audio (Left)
Audio (Right)
0111
Audio (L+R)
Audio (Left)
Audio (Right)
1000
1001
Audio (Left)
Voice + Audio
(Left)
Voice
Voice
Voice
Voice
Voice
1010
If set, resets the LM4931, excluding the I
2
C/SPI registers and PLL. SOFTRESET should
be cleared to resume normal operation.
Disables the audio DAC dither.
Audio (Left)
Audio (Left)
Mixed mode
4
SOFTRESET
5
DAC_
DITHER_OFF
BYPASS_BYPASS If set the power management and control circuit will assume that bypass is at V
DD
/2
even when such condition is false. (Note 12)
RSVD
RESERVED (Note 14)
6
7
Note 12:
It is recommended to alter this bit only while the part is in Powerdown mode.
Note 13:
Modes 8, 9, and 10 are only available if the sample rate of the I
2
S is an integer multiple of the sample rate of the PCM. For example, 48kHz (I
2
S) and 8kHz
(PCM) would be acceptable.
Note 14:
Reserved bits should be set to zero when programming the associated register.
L
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