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參數(shù)資料
| 型號： | LM4931 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Audio Subsystem with Mono High Efficiency Loudspeaker and Stereo Headphone Amplifiers |
| 中文描述： | 與單聲道音頻子系統(tǒng)高效揚聲器和立體聲耳機放大器 |
| 文件頁數(shù)： | 43/47頁 |
| 文件大?。?/td> | 1640K |
| 代理商： | LM4931 |
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Application Information
(Continued)
energy-saving power down mode, and master or slave op-
eration. PCM_SYNC is the word sync line for the bus. It may
be set in the
INTERFACES (09h)
register (bit 3 PCM-
_LONG) for short or long frame sync. A short frame sync is 1
PCM_CLK cycle (PCM_LONG=0), a long frame sync is an
inverted version of short sync (PCM_LONG=1). This is illus-
trated by
Figure 7
in the
PCM
timing diagram under the
Audio Interfaces
section. PCM_CLK is the bit clock for the
bus. Its frequency is fixed at 128kHz and may be generated
by the LM4931 when the PCM section is set to operate in
master mode by setting bit 2 of the
INTERFACES (09h)
register. Clearing this same bit (bit 2) places the PCM sec-
tion into slave mode where an external clock must be pro-
vided.
The other two lines, PCM_SDO and PCM_SDI, are for serial
data out and serial data in, respectively. The type of data
may also be set in the
INTERFACES (09h)
register by bits 0
and 1. Bit 0 controls whether the data is linear or com-
panded. If set to 1, the 8 MSBs are presumed to be com-
panded data and the 8 LSBs are ignored. If cleared to 0, the
data is treated as 2’s complement PCM data. Bit 1 controls
which PCM law is used if Bit 0 is set for companded (G711)
data. If set to 1, the companded data is assumed to beA-law.
If cleared to 0, the companded data is treated as μ-law.
I
2
S Interface Bus (JP13)
The I
2
S standard provides a uni-directional serial interface
designed specifically for digital audio. For the LM4931, the
interface provides access to a 48kHz, 18 bit full-range stereo
audio DAC. This interface uses a three port system of clock
(I
2
S_CLK), data (I
2
S_SDI), and word (I
2
S_WS). The clock
and word lines can be either master or slave as set by bit 4
in the
INTERFACES (09h)
register.
Abit clock (I
2
S_CLK) at 32 or 64 times the sample frequency
is generated by the I
2
S system master (unless set as a
slave) and a word select (I
2
S_WS) line is driven at a fre-
quency equal to the sampling rate of the audio data, up to
48kHz. The word length is set by bit 5 of the
INTERFACES
(09h)
register. When bit 5 is cleared, a word length of 16 bits
is selected. When set, the word length is set to 32 bits. All
18MSBs are passed to the DAC when the I
2
S interface is set
to 32 bit word mode. In 16 bit mode, all 16 bits are sent to the
DAC. The word line is registered to change on the negative
edge of the bit clock. The serial data (I
2
S_SDI) is sent MSB
first, again registered on the negative edge of the bit clock,
delayed by 1 bit clock cycle relative to the changing of the
word line (see
Figure 6
).
MCLK/XTAL_IN (JP3)
This is the input for an external Master Clock. The jumper at
S13 must be removed (disconnecting the onboard crystal
from the circuit) when using an external Master Clock. Addi-
tionally, the jumper S14 may be used to connect the MCLK
with the PCM and I
2
S interface buses.
High-Efficiency Class D BTL Mono Out (JP5)
This is the high-efficiency mono speaker output, designed for
use with an 8
speaker. The outputs are driven in bridge-
tied-load (BTL) mode, so both sides have signal. Outputs are
normally biased at one half AV
when the LM4931 is in
active mode. The class D amplifier provides exceptional
power use savings versus standard class AB amplifiers. A
measurement output (JP6) is also provided, since the
switching characteristics of an unfiltered Class D output
often render conventional audio measurement techniques
useless. This output band-limits the output to 20kHz, filtering
out the switching noise for measurement purposes. This
measurement output is not intended to provide power to a
load.
Stereo Headphone Out (JP15 or P1)
This is the stereo headphone output. Each channel is single-
ended, with 47uF DC blocking capacitors mounted on the
demo board. The jack (P1) features a typical stereo head-
phone pinout. An alternate, pinned connection is also pro-
vided (JP15).
Headphone sense is incorporated into the jack on the demo
board. In this application HP_SENSE is pulled low by the
1k
resistor when no headphone is present. This gives a
corresponding logic low output on the HP_SENSE pin.
When a headphone is placed in the jack the 1k
pull-down
is disconnected and a 100k
pull-up resistor creates a high
voltage condition on HP_SENSE. This information may be
placed on the GPIO pin to reliably drive an external micro-
controller with headphone status.
It is important to note that if using the alternate connection
(JP15) for stereo headphone operation, HP sense is still tied
to the mini-jack, requiring a physical plug to break the con-
nection. HP sensing will then require a plug be placed in the
jack (dummy plug).
MIC Jack (JP1)
This jack is for connection to an external microphone like the
kind typically found in mobile phones. Pin 1 is GND, pin 2 is
the negative input pin, and pin 3 is the positive pin, with
phantom voltage supplied by MIC_BIAS on the LM4931.
GPIO (JP14)
This pin provides simple status updates from the LM4931 to
an external microcontroller if desired. The GPIO output may
be configured in the
PMC_CONFIG (0Ah)
register. Bits of
the
PMC_CONFIG (0Ah)
register may be used to set the
GPIO to output information regarding whether the head-
phone is connected, the voice-codec clock, an external LS
enable signal, and shutdown status for the voiceband ADC,
voiceband DAC, and the Left and Right channels of the full
range-audio DAC. The voice-codec clock is only provided
over the GPIO port if the voice codec is enabled. These
outputs can be useful for simple software/driver develop-
ment to monitor mode changes, or as a simple debugging
tool.
BASIC OPERATION
The LM4931 is a highly integrated audio subsystem with
many different operating modes available. These modes
may be controlled in the
BASIC_CONFIG (00h)
register by
bits 3:0. These mode settings are shown in the
BASIC_CO-
NFIG (00h)
register table and are described here below:
Powerdown Mode (0000b)
Part is powered down, analog outputs are not biased. This is
a minimum current mode. All part features are shut down.
Standby Mode (0001b)
The LM4931 is powered down, but outputs are still biased at
one half AV
DD
. This comes at some current cost, but pro-
vides a much faster turn-on time with zero "click and pop"
transients on the headphone out. Standby mode can be
L
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43
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| LM49321RL | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Audio Sub-System with Stereo DAC, Mono Class AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression |
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