參數(shù)資料
型號(hào): LM4931
廠商: National Semiconductor Corporation
英文描述: Audio Subsystem with Mono High Efficiency Loudspeaker and Stereo Headphone Amplifiers
中文描述: 與單聲道音頻子系統(tǒng)高效揚(yáng)聲器和立體聲耳機(jī)放大器
文件頁(yè)數(shù): 21/47頁(yè)
文件大?。?/td> 1640K
代理商: LM4931
Clock Divider Configuration Registers
This register is used to control the multiplexers in the clock module.
DEFAULT CHART FOR CLK_MUX (08h)
DATA BIT
DEFAULT
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
CLK_MUX (08h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
Description
0
PLL_INPUT
Programs the PLL input multiplexer to select. (Note 12)
PLL_INPUT
0
1
If set the master clock is divided by two, for example allowing for a
24.576MHz or PCI clock to be used. (Note 12, 15)
FAST_CLOCK
0
1
Selects which clock is passed to the audio sub-system: (Note 12)
AUDIO_CLK_SEL
PLL Input Source
MCLK
I
2
S Input Clock
1
FAST_CLOCK
MCLK Frequency
Normal
Divided by 2
2
AUDIO_CLK_SEL
Audio Sub-system
Input Source
PLL Output
MCLK / MCLK/2
0
1
3
VOICE_CLK_SEL
Selects which clock is passed to the voice sub-system: (Note 12)
VOICE_CLK_SEL
Audio Sub-system
Input Source
PLL Output
MCLK / MCLK/2
0
1
4
PLL_DISABLE
Powers down the PLL if it is not required.
Programs the Q divider (divides from the PLL output frequency of
12.288MHz).
6:5
00
01
10
11
RESERVED (Note 14)
6:5
Q_DIV
Divide Value
12 (1.024MHz/8kHz)
8 (1.536MHz/12kHz)
6 (2.048MHz/16kHz)
4 (3.072MHz/24kHz)
7
RSVD
Note 15:
For inputs greater than 50Mhz, the input clock divider FAST_CLOCK should be set.
L
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