參數(shù)資料
型號(hào): LM4931
廠商: National Semiconductor Corporation
英文描述: Audio Subsystem with Mono High Efficiency Loudspeaker and Stereo Headphone Amplifiers
中文描述: 與單聲道音頻子系統(tǒng)高效揚(yáng)聲器和立體聲耳機(jī)放大器
文件頁(yè)數(shù): 24/47頁(yè)
文件大?。?/td> 1640K
代理商: LM4931
Power Management Configuration Registers
This register is used to control the power management settings.
DEFAULT CHART FOR PMC_CONFIG (0Ah)
DATA BIT
DEFAULT
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
PMC_CONFIG (0Ah) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
Description
0
ZXD_DISABLE
If set then zero cross detection is ignored when changing modes or
gains. (Note 19)
Set to accommodate a selected bypass capacitor value to give correct
turn-on delay and click/pop performance. Value is set as follows: (Note
17)
2:1
Delay
00
short
01
medium
10
11
Set the GPIO port function: (Note 18)
5:3
000
001
010
011
100
101
110
111
RESERVED (Note 14)
When set enables dither in the class D amplifier
2:1
CAP_SIZE
Capacitor Size/Time
0.1μF/25ms
1μF/100ms
2.2μF/200ms
Test Mode/1ms
long
test
5:3
GPIO_SETUP
GPIO
HP_CONNECTED
VC_CLOCK
GPIO_DATA
EXT_LS_ENABLE
VOICE_ADC_SD
VOICE_DAC_SD
DAC_LEFT_SD
DAC_RIGHT_SD
6
7
RSVD
CLASS_D_DITHER
Note 17:
The effect of CAP_SIZE will vary with the audio clock frequency. The delays quoted are for a 12.288MHz MCLK. These will scale inversely to the MCLK
frequency. For example if used in a 44.1kHz application where the PLL output is 11.2896MHz, “01” or 100ms will be 100ms*11.2896/12.288 = 108.8ms. It is
suggested that to save power earlier during the shutdown cycle, the PLL can be disabled and the MCLK or MCLK/2 can be used to bypass the PLL and also provide
longer shutdown times for further reduced click and pop.
Note 18:
VC_CLOCK is only supplied over the GPIO port if the voice codec is enabled.
Note 19:
To ensure a successful transition into Powerdown Mode, ZXD_DISABLE must be set whenever there is no audio input signal present.
L
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