參數(shù)資料
型號(hào)： LPC2290
廠商： NXP Semiconductors N.V.
英文描述： 16/32-bit ARM microcontrollers with CAN, 10-bit ADC and external memory interface
中文描述： 與CAN，16/32位ARM微控制器的10位模數(shù)轉(zhuǎn)換器和外部存儲(chǔ)器接口
文件頁(yè)數(shù)： 22/41頁(yè)
文件大?。?/td> 185K
代理商： LPC2290
Philips Semiconductors
LPC2290
16/32-bit ARM microcontrollers with external memory interface
Preliminary data
Rev. 01 — 09 February 2004
22 of 41
9397 750 12874
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.16 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. It also includes four capture inputs to trap the timer value when an
input signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an application with
‘or’ and ‘a(chǎn)nd’, as well as ‘broadcast’ functions among them.
6.16.1
Features
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
Four 32-bit match registers that allow:
–
Continuous operation with optional interrupt generation on match.
–
Stop timer on match with optional interrupt generation.
–
Reset timer on match with optional interrupt generation.
Four external outputs per timer corresponding to match registers, with the following
capabilities:
–
Set LOW on match.
–
Set HIGH on match.
–
Toggle on match.
–
Do nothing on match.
6.17 Watchdog timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, the Watchdog will
generate a system reset if the user program fails to ‘feed’ (or reload) the Watchdog
within a predetermined amount of time.
6.17.1
Features
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to
be disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate Watchdog reset.
Programmable 32-bit timer with internal pre-scaler.
Selectable time period from (t
pclk
×
256
×
4) to (t
pclk
×
2
32
×
4) in multiples of
t
pclk
×
4.
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