參數(shù)資料
型號: LPC2290
廠商: NXP Semiconductors N.V.
英文描述: 16/32-bit ARM microcontrollers with CAN, 10-bit ADC and external memory interface
中文描述: 與CAN,16/32位ARM微控制器的10位模數(shù)轉(zhuǎn)換器和外部存儲器接口
文件頁數(shù): 23/41頁
文件大?。?/td> 185K
代理商: LPC2290
Philips Semiconductors
LPC2290
16/32-bit ARM microcontrollers with external memory interface
Preliminary data
Rev. 01 — 09 February 2004
23 of 41
9397 750 12874
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.18 Real time clock
The Real Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use
little power, making it suitable for battery powered systems where the CPU is not
running continuously (Idle mode).
6.18.1
Features
Measures the passage of time to maintain a calendar and clock.
Ultra Low Power design to support battery powered systems.
Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
Programmable Reference Clock Divider allows adjustment of the RTC to match
various crystal frequencies.
6.19 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2290. The Timer is designed to count
cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform
other actions when specified timer values occur, based on seven match registers. The
PWM function is also based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to
be used for more applications. For instance, multi-phase motor control typically
requires three non-overlapping PWM outputs with individual control of all three pulse
widths and positions.
Two match registers can be used to provide a single edge controlled PWM output.
One match register (MR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single
edge controlled PWM outputs require only one match register each, since the
repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM
outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0
match occurs.
Three match registers can be used to provide a PWM output with both edges
controlled. Again, the MR0 match register controls the PWM cycle rate. The other
match registers control the two PWM edge positions. Additional double edge
controlled PWM outputs require only two match registers each, since the repetition
rate is the same for all PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising
and falling edge of the output. This allows both positive going PWM pulses (when the
rising edge occurs prior to the falling edge), and negative going PWM pulses (when
the falling edge occurs prior to the rising edge).
6.19.1
Features
Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
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