參數(shù)資料
型號: LPC2290
廠商: NXP Semiconductors N.V.
英文描述: 16/32-bit ARM microcontrollers with CAN, 10-bit ADC and external memory interface
中文描述: 與CAN,16/32位ARM微控制器的10位模數(shù)轉(zhuǎn)換器和外部存儲器接口
文件頁數(shù): 24/41頁
文件大?。?/td> 185K
代理商: LPC2290
Philips Semiconductors
LPC2290
16/32-bit ARM microcontrollers with external memory interface
Preliminary data
Rev. 01 — 09 February 2004
24 of 41
9397 750 12874
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The match registers also allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled PWM outputs.
Single edge controlled PWM outputs all go HIGH at the beginning of each cycle
unless the output is a constant LOW. Double edge controlled PWM outputs can
have either edge occur at any position within a cycle. This allows for both positive
going and negative going pulses.
Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs
will occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive
going or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation
of erroneous pulses. Software must ‘release’ new match values before they can
become effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
6.20 System control
6.20.1
Crystal oscillator
The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator
output frequency is called f
osc
and the ARM processor clock frequency is referred to
as cclk for purposes of rate equations, etc. f
osc
and cclk are the same value unless
the PLL is running and connected. Refer to
Section 6.20.2 “PLL”
for additional
information.
6.20.2
PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The
input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in
practice, the multiplier value cannot be higher than 6 on this family of microcontrollers
due to the upper frequency limit of the CPU). The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO
within its frequency range while the PLL is providing the desired output frequency.
The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock.
Since the minimum output divider value is 2, it is insured that the PLL output has a
50% duty cycle.The PLL is turned off and bypassed following a chip Reset and may
be enabled by software. The program must configure and activate the PLL, wait for
the PLL to Lock, then connect to the PLL as a clock source.
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