參數(shù)資料
型號: LRS1341
廠商: Sharp Corporation
英文描述: Stacked Chip 16M Flash Memory and 2M SRAM
中文描述: 堆疊芯片1,600快閃記憶體以及2M SRAM
文件頁數(shù): 3/24頁
文件大小: 197K
代理商: LRS1341
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
Data Sheet
3
Table 1. Pin Descriptions
PIN
DESCRIPTION
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
A
0
to A
16
F-A
17
to F-A
19
F-CE
S-CE
1
, S-CE
2
F-WE
S-WE
F-OE
S-OE
S-LB
S-UB
Address Inputs (Common)
Address Inputs (Flash)
Chip Enable Input (Flash)
Chip Enable Inputs (SRAM)
Write Enable Input (Flash)
Write Enable Input (SRAM)
Output Enable Input (Flash)
Output Enable Input (SRAM)
SRAM Byte Enable Input (DQ
0
to DQ
7
)
SRAM Byte Enable Input (DQ
8
to DQ
15
)
Reset/Power Down (Flash)
Block erase and Word Write: V
IH
or V
HH
Read: V
IH
or V
HH
Reset/Power Down: V
IL
Write Protect (Flash)
Two Boot Blocks Locked: V
IL
(with F-RP = V
HH
Erase of Write can operate to all blocks)
Ready/Busy (Flash)
During an Erase or Write operation: V
OL
Block Erase and Word Write Suspend: HIGH-Z
Deep Power Down: V
OH
Data Input/Outputs (Common)
Power Supply (Flash)
Power Supply (SRAM)
Write, Erase Power Supply (Flash)
Block Erase and Word Write: F-V
PP
= V
PPLK
All Blocks Locked: F-V
PP
< V
PPLK
Ground (Common)
No Connection
Test Pins (Should be Open)
F-RP
Input
F-WP
Input
F-RY/BY
Output
DQ
0
to DQ
15
F-V
CC
S-V
CC
Input/Output
Power
Power
F-V
PP
Power
GND
NC
T
1
to T
5
Power
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