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參數(shù)資料
| 型號： | LT8500IUHH#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 0K |
| 描述： | IC PWM GENERATOR 56-QFN |
| 標準包裝： | 40 |
| 類型： | PWM 發(fā)生器 |
| PLL： | 無 |
| 主要目的： | LED 照明 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 0.075 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 50MHz |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 56-QFN-EP（5x9） |
| 包裝： | 管件 |
LT8500
18
8500f
applicaTions inForMaTion
This section is illustrated with an LED dimming applica-
tion, but is relevant to other applications as well. The
LT8500 provides 48 PWM outputs, such as for driving
three LT3595A LED drivers. The LT8500 provides an LED
dot correction function using digital multiplication of the
correction register (COR) and the PWM update value,
which is prescaled by 2/3. This results in a dot corrected
PWM duty cycle. Optionally, the PWM update can be
written directly (unchanged) by setting the correction
register disable bit (CMD = 0x7X). When this bit is set,
the multiplication is bypassed and dot correction, if any,
must be calculated off-chip. The PWM duty cycle in this
case will be the nominal value sent in the update frame,
divided by 4096. The part provides a status frame with
OPENLED and COR data for each channel, and global state
data indicating self testing (such as for open LED’s), out-
of-sync error, phase-shift status, and direct data status.
The status frame is shifted out of the part whenever a new
frame is shifted in. An on-chip self test is available (CMD
= 0x5X) to determine which channel is responsible for a
fault, such as open LEDs. The OPENLED pin and self test
are especially suited for use with the LT3595A. In this
application, the self test will identify which channels have
opens in their LED strings. This Applications Information
section serves as a guideline for avoiding common pitfalls
for the typical application.
Setting Grayscale by PWM Updates
Although adjusting the LED current changes its luminous
intensity, or brightness, it will also affect the color match-
ing between LED channels by shifting the chromaticity
coordinate. The best way to adjust the brightness is to
control the amount of LED on/off time by pulse width
modulation (PWM).
The LT8500 can adjust the brightness for each channel
independently. The 12-bit PWM registers (PWMR), used
for grayscale (GS) dimming, results in 4095 different
brightness steps from 0% to 99.98%. The brightness
level, or PWM duty cycle, GSn% for channel n can be
calculated as:
GSn%=
GSRn(CALC)
4096
100%
where GSRn(CALC)is the nth calculated grayscale register
(same as PWMR) setting (GSRn(CALC) = 0 to 4052 with
dot correction enabled).
Setting Dot Correction
The LT8500 can adjust the PWM duty cycle for each chan-
nel independently. The duty cycle adjustment, also called
dot correction, is mainly used to calibrate the brightness
deviation between LED channels. The 6-bit (64 values) dot
correctionregisters(DCR,sameasCOR)adjusteachPWM
duty cycle from 0.5X to ~1.5X of the duty cycle, prescaled
by 2/3, sent to the grayscale register (GSR) according to
PWMOUTn = CHANn (NOM)
2
3
CORn + 32
64
where PWMOUTn is the nth PWM duty cycle, GSRn(NOM)
is the nominal grayscale value sent to the nth channel
and DCRn is the nth programmed dot correction setting
(DCRn = 0 to 63).
Cascading Devices and Determining Serial Data
Interface Clock
In a large LCD backlighting or LED display system, mul-
tiple LT8500 chips can be easily cascaded to drive all LED
drivers, such as the LT3595A, and their associated LED
strings. The LT8500 adopts a novel 5-wire topology, which
balances clock skew and eases PCB layout.
The time required to send a set of cascaded frames is 584
SCKI cycles per LT8500, plus another cycle time for LDI.
Assuming LDI is externally balanced, the minimum serial
data interface clock frequency SCK for a large display
system can be calculated as:
SCK = [(nCHIPS 584) + 1] REFRESH
where nCHIPS is the number of cascaded LT8500s and
REFRESH is the refresh rate of the whole system.
Status Frame Information
The status frame is captured and shifted out of SDO as a
new data frame shifts in on SDI. The format of a status
frame is shown in Figure 5. With the exception of the
diagnostic flags (SYC and NOL[48:1]), the data in the
status frame does not change without a command from
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