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參數(shù)資料
| 型號： | LT8500IUHH#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PWM GENERATOR 56-QFN |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類型： | PWM 發(fā)生器 |
| PLL： | 無 |
| 主要目的： | LED 照明 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 0.075 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 50MHz |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-QFN-EP（5x9） |
| 包裝： | 管件 |
LT8500
16
8500f
operaTion
Phase-Shift Toggle Frame: CMD = 0x6X
Thephase-shifttoggleframetogglesthephase-shift(PHS)
bit, which is off by default. When PHS is set, it sets the
rising edges of the PWM outputs, by banks of 16 chan-
nels, out-of-phase with each other by 120 degrees. This
meansthatchannelsPWM[48:33]willstartthePWMcycle
with a rising edge at the beginning of a PWM period, then
channels PWM[32:17] will start their PWM cycle 1/3 of
the time into a PWM period, and channels PWM[16:1] will
start 2/3 of the time into a PWM period. The state of the
PHS bit is returned in every status frame. The data in the
phase-shift toggle frame is irrelevant to the command,
but allows a daisy chain of LT8500’s to function properly.
Correction Toggle Frame: CMD = 0x7X
Thecorrectiontoggleframetogglesthecorrectionregister
disable (CRD) bit, which is off by default. When CRD is set,
it disables use of the correction registers (CORs) in the
correctionmultiplier,insteadmultiplyingtheincomingdata
from SDI by “1.” This causes the data in an update frame
to reach the PWMRSYNC registers unchanged. The state
of the CRD bit is returned in every status frame. The data in
the correction toggle frame is irrelevant to the command,
but allows a daisy chain of LT8500’s to function properly.
Examples of PWM Updates for Selected Cases
Figure6showsexamplesoftheeffectofvariouscommands
onthePWMoutputwaveforms.Theseexamplewaveforms
assume all three channels shown are always programmed
for the same PWM width. For each case, a representative
channel is shown from each of the three 16 channel banks,
PWM[48:33], PWM[32:17], and PWM[16:1].
CaseAillustratesthephase-shiftmodeinsteady-state,with
PWM’s programmed for a width of 256 PWMCK cycles.
PWM[48], from bank 2, rises at the beginning of the PWM
period. PWM[32], from bank 1, rises 1/3 of the way into
the PWM period of bank 2, or 1365 PWMCK cycles later.
PWM[16], from bank 0, rises 2/3 of the way into the PWM
period of bank 2, or 2730 PWMCK cycles later.
Case B illustrates a synchronous update frame (CMD =
0x0X) while in phase-shift mode, as in case A. The LDI
signal goes active 512 PWMCK cycles into the PWM
period, after PWM[48] has turned off. The update frame
programs a PWM width of 1024, but the synchronous
update command prevents a channel from updating
except at the beginning of its PWM period. As a result,
PWM[48] remains low until the next PWM period, when
the updated width drives it high for 1024 PWMCK cycles.
PWM[32] begins its PWM period at PWMCK 1365, and
PWM[16] starts at PWMCK 2730, both updated to 1024
PWMCK cycles.
Case C illustrates an asynchronous update frame (CMD
= 0x1X) while in phase-shift mode, as in case A. The LDI
signalgoesactive512PWMCKcyclesintothePWMperiod,
afterPWM[48]hasturnedoff. Theupdateframeprograms
a PWM width of 1024, and because it is an asynchronous
update, PWM[48] immediately rises and stays high until
PWMCK 1024. PWM[32] and PWM[16] (and all PWM’s)
are also updated, but no rising edge occurs until their
PWM period begins due to the phase-shifting.
Case D illustrates the default (not phase-shifted) mode in
steady-state. All PWM outputs rise on the same PWMCK
edge at the beginning of the PWM period.
Case E illustrates a synchronous update frame (CMD =
0x0X) without phase-shifting, as in case D. The LDI signal
goes active 512 PWMCK cycles into the PWM period, after
the PWMs have turned off. The update programs a PWM
width of 1024, but the synchronous update command
prevents a channel from updating except at the beginning
of it’s PWM period. As a result, all PWM’s remain low until
the next PWM period, when the updated width drives them
high for 1024 PWMCK cycles.
Case F illustrates an asynchronous update frame (CMD =
0x1X) without phase-shifting, as in case D. The LDI signal
goes active 512. PWMCK cycles into the PWM period, after
the PWMs have turned off. The update programs a PWM
widthof1024,andbecauseitisanasynchronousupdate,all
PWM’s immediately rise and stay high until PWMCK 1024.
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