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參數(shù)資料
| 型號(hào)： | LT8500IUHH#PBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 24/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PWM GENERATOR 56-QFN |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類型： | PWM 發(fā)生器 |
| PLL： | 無(wú) |
| 主要目的： | LED 照明 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 0.075 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 50MHz |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-QFN-EP（5x9） |
| 包裝： | 管件 |
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LT8500
9
8500f
operaTion
START-UP
The LT8500 is ready to communicate after power-up, if
the LDIBLANK pin is low. The PWM[48:1] outputs remain
disabled (logic 0) until an output enable frame is sent. The
recommended sequence of events for start-up is:
1. Apply power and drive LDIBLANK low. SDO will go low
when the on-chip power-on-reset (POR) de-asserts.
2. Send a correction register frame (CMD = 0x20) on the
serial interface. This sets the correction factor on each
channel.
3. Send an update frame (CMD = 0x00 or CMD = 0x10)
on the serial interface. This sets the pulse width of each
channel.
4. Send an output enable frame (CMD = 0x30) on the
serial interface. This enables the modulated pulses on
the PWM[48:1] outputs.
The PWM clock (PWMCK) should be turned on before
step 4. The start of a PWM period, when all PWM[48:1]
channels turn on, is synchronized to the output enable
frame when the outputs are disabled prior to the frame.
Figure 2. Serial Interface Topologies
SERIAL DATA INTERFACE
The LT8500 has a 50MHz cascadable serial data interface
with full buffering and skew balancing on clock and data.
The interface uses a novel 5-wire (LDIBLANK, SCKI, SDI,
SCKO, and SDO) topology and can be connected to a
variety of digital controllers, such as microcontrollers,
digital signal processors (DSPs), or field programmable
gate arrays (FPGAs).
Topology
Two topologies shown in Figure 2 are supported for cas-
cading the LT8500. For higher speeds and a large number
of LT8500s, consider the novel 5-wire topology. For lower
speedsandfewLT8500s,considertheconventional4-wire
topology. Whichever topology is used, signal integrity
should be carefully evaluated, especially for the clocks.
The 5-wire topology eliminates the need for global SCKI
routing and reduces the need for buffer insertion for the
SCKI signal. Instead, it provides the SCKO signal along
with the SDO signal to drive the next chip. The skew inside
the chip between the SCKI and SDI signals is balanced
internally. The skew outside the chip between the SCKO
and SDO signals can be easily balanced by parallel routing
8500 F02
LDI
SCKI
SDI
SCK0
SDO
HOST
CONTROLLER
LDI
SCKI
SDI
SDO
SCKO
LT8500 (1)
LDI
SCKI
SDI
SCK0
SDO
LT8500 (2)
LDI
SCKI
SDI
SCK0
SDO
LT8500 (N)
LDI
SCKI
SDI
SDO
HOST
CONTROLLER
Conventional 4-Wire Topology
Novel 5-Wire Topology
LDI
SCKI
SDI
SDO
LT8500 (1)
LDI
SCKI
SDI
SDO
LT8500 (2)
LDI
SCKI
SDI
SDO
LT8500 (N)
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