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參數(shù)資料
| 型號： | LT8500IUHH#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 21/24頁 |
| 文件大小： | 0K |
| 描述： | IC PWM GENERATOR 56-QFN |
| 標準包裝： | 40 |
| 類型： | PWM 發(fā)生器 |
| PLL： | 無 |
| 主要目的： | LED 照明 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 0.075 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 50MHz |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 56-QFN-EP（5x9） |
| 包裝： | 管件 |
LT8500
6
8500f
pin FuncTions
PWM[48:1](Pins1to33,42to56):PulseWidthModulated
(PWM) Output Pins. Pulse width is determined by com-
paring the value in the PWMRSYNC latches to an internal
PWMCK counter. Outputs are high when the value in the
PWMCK counter is less than the value in PWMRSYNC[n].
The PWM frequency is determined by the signal applied
to the PWMCK pin.
OPENLED (Pin 34): Not Open LED Input Pin. This input
passes diagnostic information to the host via the status
frame. When used with LT3595A LED drivers, it connects
to the wired-OR (open collector) OPENLED outputs which
indicate an open in one or more of the LED strings. The
user can run a self test on the LT8500 to detect which
PWM output is associated with an open LED string, or
other fault. This pin has an internal 100kΩ pull-up to the
VCC supply rail.
SDO (Pin 35): Serial Data Output Pin. This pin is the output
oftheshiftregister(SR),andcascadesdatatodownstream
chips or returns data to the host.
SCKI (Pin 36): Serial Clock Input Pin. This clock pin pro-
vides timing for the serial interface and the calculation
of PWM values in the correction multiplier. This clock is
independent of PWMCK.
VCC (Pin 37): Supply Pin. 3.0V to 5.5V. Must be locally
bypassed with a capacitor to ground.
SCKO (Pin 38): Serial Clock Output Pin. Buffered pass
through of SCKI. This pin cascades the clock to the next
chip or to the host.
PWMCK (Pin 39): PWM Clock Input Pin. This pin provides
PWM timing for the outputs. Each PWM signal is gener-
ated by counting the pulses on this clock from zero to
the calculated value in the PWM synchronization register
(PWMRSYNC). This clock is independent of SCKI.
SDI (Pin 40): Serial Data Input Pin. This pin provides
serial interface data to issue commands and set up the
individual PWM channels.
LDIBLANK (Pin 41): Latch Data In/Blank Input Pin. This
is a dual function pin.
LDI Function: The internal LDI signal is directly con-
nected to the LDIBLANK pin. A logic high on the pin
always asserts the LDI function. The rising edge of
LDIBLANK captures the decoded command field (CMD,
CR[7:0]) of the shift register (SR[7:0]). The high level
ofLDIBLANKlatchesdatafromthecorrectionmultiplier
into the PWM Registers (PWMR). When LDIBLANK is
high, status information is loaded into the shift register
(SR) to shift out on SDO when the next frame shifts in
on SDI. See more details in the Operation section.
BLANK Function: Asserting LDIBLANK high for more
than 50s turns off all PWM[48:1] outputs and resets
the chip. To avoid inadvertently resetting the chip, do
not assert LDIBLANK high for more than 5s.
GND (Exposed Pad Pin 57): This is the ground reference
for the chip.
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