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參數(shù)資料
| 型號： | LU3X31T-T64 |
| 廠商： | Lineage Power |
| 英文描述： | Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（單端口3伏1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 1/44頁 |
| 文件大?。?/td> | 580K |
| 代理商： | LU3X31T-T64 |
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Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Overview
The LU3X31T-T64 is a fully integrated
10/100 Mbits/s physical layer device with an inte-
grated transceiver. It is provided in a 64-pin TQFP
package with low-power operation and powerdown
modes. Typical applications for this part are CardBus
and PCMCIA Ethernet products. Operating at 3.3 V,
the LU3X31T-T64 is a powerful device for the forward
migration of legacy 10 Mbits/s products and noncom-
pliant (does not have autonegotiation) 100 Mbits/s
devices. The LU3X31T-T64 was designed from the
beginning to conform fully with all pertinent specifica-
tions, from the ISO
*
/IEC 11801 and EIA
/TIA 568
cabling guidelines to ANSI
X3.263 TP-PMD to
IEEE
§
802.3 Ethernet specifications.
Features
I
Single-chip integrated physical layer and trans-
ceiver for 10Base-T and/or 100Base-T functions
I
IEEE 802.3 compatible 10Base-T and 100Base-T
physical layer interface and ANSIX3.263 TP-PMD
compatible transceiver
I
Built-in analog 10 Mbits/s receive filter, eliminating
the need for external filters
I
Built-in 10 Mbits/s transmit filter
I
10 Mbits/s PLL exceeding tolerances for both pre-
amble and data jitter
I
100 Mbits/s PLL, combined with the digital adap-
tive equalizer, robustly handles variations in rise-
fall time, excessive attenuation due to channel
loss, duty-cycle distortion, crosstalk, and baseline
wander
I
Transmit rise-fall time can be manipulated to pro-
vide lower emissions, amplitude fully compatible
for proper interoperability
I
Programmable scrambler seed for better FCC
compliancy
I
IEEE 802.3u Clause 28 compliant autonegotiation
for full 10 Mbits/s and 100 Mbits/s control
I
Fully configurable via pins and management
accesses
I
Extended management support with interrupt
capabilities
I
PHY MIB support
I
Symbol mode option
I
Low-power operation: <150 mA max
I
Low autonegotiation power: <30 mA
I
Very low powerdown mode: <5 mA
I
64-pin TQFP package (10 mm x 10 mm x 1.4 mm)
* ISO is a registered trademark of The International Organization
for Standardization.
EIAis a registered trademark of The Electronic Industries Asso-
ciation.
ANSIis a registered trademark of The American National Stan-
dards Institute, Inc.
§IEEE s a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
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