參數資料
型號: LU3X31T-T64
廠商: Lineage Power
英文描述: Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網收發(fā)器)
中文描述: 單端口3伏10/100以太網收發(fā)器德克薩斯州/外匯(單端口3伏1000萬位和100米位以太網收發(fā)器)
文件頁數: 23/44頁
文件大小: 580K
代理商: LU3X31T-T64
Lucent Technologies Inc.
23
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers
(continued)
Table 14. Status Register (Register 1h)
Bit(s)
Name
Description
R/W
RO
Default
0h
15
100Base-T4
1
Capable of 100Base-T4.
0
Not capable of 100Base-T4.
This bit is hardwired to 0, indicating that the
LU3X31T-T64 does not support 100Base-T4.
1
Capable of 100Base-X full-duplex mode.
0
Not capable of 100Base-X full-duplex
mode.
This bit is hardwired to 1, indicating that the
LU3X31T-T64 supports 100Base-X full-
duplex mode.
1
Capable of 100Base-X half-duplex mode.
0
Not capable of 100Base-X half-duplex
mode.
This bit is hardwired to 1, indicating that the
LU3X31T-T64 supports 100Base-X half-
duplex mode.
1
Capable of 10 Mbits/s full-duplex mode.
0
Not capable of 10 Mbits/s full-duplex
mode.
This bit is hardwired to 1, indicating that the
LU3X31T-T64 supports 10Base-T full-duplex
mode.
1
Capable of 10 Mbits/s half-duplex mode.
0
Not capable of 10 Mbits/s half-duplex
mode.
This bit is hardwired to 1, indicating that the
LU3X31T-T64 supports 10Base-T half-duplex
mode.
1
Capable of 100Base-T2.
0
Not capable of 100Base-T2.
This bit is hardwired to 0, indicating that the
LU3X31T-T64 does not support 100Base-T2.
Ignore when read.
1
Accepts management frames with pre-
amble suppressed.
0
Will not accept management frames with
preamble suppressed.
This bit is hardwired to 1, indicating that the
LU3X31T-T64 accepts management frame
without preamble. A minimum of 32 pre-
amble bits are required following power-on or
hardware reset. One IDLE bit is required
between any two management transactions
as per IEEE802.3u specification.
14
100Base-X Full-duplex
RO
1h
13
100Base-X Half-duplex
RO
1h
12
10 Mbits/s Full-duplex
RO
1h
11
10 Mbits/s Half-duplex
RO
1h
10
100Base-T2
RO
0h
9:7
6
Reserved
RO
RO
0h
1h
MF Preamble Suppression
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