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參數(shù)資料
| 型號： | LU3X31T-T64 |
| 廠商： | Lineage Power |
| 英文描述： | Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（單端口3伏1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 29/44頁 |
| 文件大?。?/td> | 580K |
| 代理商： | LU3X31T-T64 |
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Lucent Technologies Inc.
29
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers
(continued)
Table 23. PHY Address Register (Register 19h)
Table 24. Config 10 Register (Register 1Ah)
Bit(s)
15:11
10:5
Name
Reserved
User Seed
Description
R/W
RO
R/W
Default
0h
21h
Reserved.
User-modifiable seed data. When the
load seed bit (bit 4 of register 18h) is set,
bits 15 through 5 of this register are
loaded into the 100Base-X scrambler.
These 5 bits store the part address used
by the serial management interface. PHY
address of 0 has the special function of
isolating the part from the MII. These bits
are initialized to the logic levels of
PHY[4:0] pins at powerup or reset.
4:0
PHY Address
R/W
Pin
Bit(s)
15
14
Name
Reserved
Description
R/W
RO
R/W
Default
0h
0h
Reserved.
1
Force 10 Mbits/s good link.
0
Normal operation.
Reserved.
1
Signal quality error test disabled.
0
Normal operation.
1
Low squelch level selected.
0
Normal squelch level selected.
1
Jabber function disabled.
0
Normal operation.
Reserved.
1—Powers down the LU3X31T-T64 com-
pletely. The part comes out of this
mode after a reset is asserted and
deasserted.
0—Normal operation.
Reserved.
1—Disable autopolarity function.
0—Enable autopolarity function.
Reserved.
Force 10 Mbits/s Good
Link
Reserved
SQE Disable
13
12
RO
R/W
0h
0h
11
Low Squelch Select
R/W
0h
10
Jabber Disable
R/W
0h
9:7
6
Reserved
Powerdown Mode
RO
R/W
0h
0h
5:4
3
Reserved
RO
R/W
0h
0h
Autopolarity Disable
2:0
Reserved
RO
0h
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