參數(shù)資料
型號: LU6612-T64-DB
英文描述: LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX
中文描述: LU6612 FASTCAT商標(biāo)單的10BASE-T/100BASE-TX快速以太網(wǎng)場效應(yīng)管
文件頁數(shù): 28/36頁
文件大小: 528K
代理商: LU6612-T64-DB
LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet
July 2000
28
Lucent Technologies Inc.
Timing Characteristics (Preliminary)
(continued)
Table 27. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK
5-5293(F).mr1
Figure 10. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK
Table 28. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK
5-5293(F).nr1
Figure 11. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK
Name
t15
t16
t17
t18
Parameter
Min
40
800
200
400
Max
500
2300
550
1000
Unit
ns
ns
ns
ns
RX/RY Activity to CRS Assertion
RX/RY Activity to RX_CLK Valid
IDL to CRS Deassertion
Dead Signal to CRS Deassertion
Name
t19
t20
t21
t22
t23
Parameter
Min
50
5
1000
50
250
Max
400
1900
1700
300
350
Unit
ns
ns
ns
ns
ns
TX_EN Asserted to Transmit Pair Activity
TX_EN Asserted to CRS Asserted Due to Internal Loopback
TX_EN Asserted to RX_CLK Valid Due to Internal Loopback
TX_EN Deasserted to IDL Transmission
IDL Pulse Width
RX/RY
CRS
(RECEIVE—START OF PACKET)
(RECEIVE—END OF PACKET)
(RECEIVE—DEAD SIGNAL)
(NOT IDL)
IDL
t15
t17
t16
t18
RX_CLK
TX/TY
CRS
(TRANSMIT—START OF PACKET)
(TRANSMIT—END OF PACKET)
IDL
t19
t22
t20
t21
t23
TX_EN
RX_CLK
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