參數(shù)資料
型號(hào)： LU6612
廠商： Lineage Power
英文描述： Single-FET for 10Base-T/100Base-TX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX 的單快速以太網(wǎng)收發(fā)器)
中文描述： 單為10BASE-T/100BASE-TX快速以太網(wǎng)場(chǎng)效應(yīng)晶體管（應(yīng)用于10基數(shù)- T的和100基數(shù)，得克薩斯州的單快速以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 12/36頁(yè)
文件大?。?/td> 528K
代理商： LU6612
LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet
July 2000
12
Lucent Technologies Inc.
Pin Information
(continued)
Table 5. Miscellaneous Pins (20)
(continued)
Signal
SPEED-
LED/
PHYAD[2]
Type
*
I/O
Pin
56
Description
Speed LED.
This pin indicates the operating speed of LU6612:
I
LED is active when in 100 Mbits/s operation.
I
LED is not active when in 10 Mbits/s operation.
At powerup/reset, this pin is sampled as input and to set the PHYAD[2] bit. If pulled
high through a resistor, this pin will set PHYAD[2] to a high or if pulled low through a
resistor, will set PHYAD[2] to a zero. When this pin is pulled high, the LED output will
be active-low, when pulled low, the LED output will be active-high.
Full-Duplex LED.
This pin indicates the operating mode of LU6612 and is only valid
when link is up:
I
LED is active when in full-duplex mode of operation.
I
LED is not active when in half-duplex mode of operation.
At powerup/reset, this pin is sampled as an input to set the PHYAD[3] bit. If pulled
high through a resistor, this pin will set PHYAD[3] to a high or if pulled low through a
resistor, will set PHYAD[3] to a zero. When this pin is pulled high, the LED output will
be active-low, when pulled low, the LED output will be active-high.
PHYAD[4].
At powerup/reset, this pin is sampled as an input to set the PHYAD[4] bit.
If pulled high through a resistor, this pin will set PHYAD[4] to a high or if pulled low
through a resistor, will set PHYAD[4] to a zero.
This pin has an internal 100
k
pull-
up resistor.
52:50
Mode Selection.
These pins carry encoded signals that are latched into the LU6612
upon powerup/reset and define specific modes of operation: half/full duplex, autone-
gotiation enabled/disabled, and transceiver isolation. Refer to Table 20 for the various
modes and how various registers are affected. Pins [52:50] have internal 100 k
pull-
ups. If left floating, LU6612 will default to all capable, autonegotiation enabled mode.
15
Test Enable Pin for Factory Testing.
This pin has an internal 100 k
pull-down
resistor. The pin can be either left floating or tied down.
19,
16
resistors. These pins can either be left floating or tied low.
12
Clock Reference.
Connect this pin to a 1 nF
±
10% capacitor to ground.
27
Full Chip Reset (Active-Low).
Reset is an active-low signal. Reset must be
asserted low for at least five LSCLK cycles. The LU6612 will come out of reset after
400
μ
s. LSCLK1 must remain running during reset.
57:58
Band-Gap Reference.
Connect these pins to a 24.9 k
±
1% resistor to ground. The
parasitic load capacitance should be less than 15 pF.
2
Current Set 100 Mbits/s.
An external reference resistor (24.9 k
) is placed from this
pin to ground to set the 100 Mbits/s TP driver transmit output level.
24
Current Set 10 Mbits/s.
An external reference resistor (22.1 k
) is placed from this
pin to ground to set the 10 Mbits/s TP driver transmit output level.
18
PCS Enable (Active-Low).
When this pin is active-low, the encoded 5-bit symbols
appear on RXD[4:0] and TXD[4:0]. When this pin high, 4-bit data appears on
RXD[3:0] and TXD[3:0]. When PCSEN is low, LU6612 bypasses the 4B5B encoder/
decoder, the align function, the scrambler/descrambler, and does not detect and gen-
erate J/K and R/T code groups at the start or end of frame. This pin has an internal
100 k
pull-up.
FUDU-
PLED/
PHYAD[3]
I/O
55
PHYAD[4]
I
↑
17
MODE[2:0]
I
↑
TEST[0]
I
↑
TEST[2:1]
I
↓
Test Enable Pin for Factory Testing.
These two pins have internal 50 k
pull-down
CLKREF
RESET
I
I
BGREF[1:0]
I
ISET_100
I
ISET_10
I
PCSEN
I
↑
*
↑
indicates there is an internal pull-up;
↓
indicates there is an internal pull-down.
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