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參數(shù)資料
| 型號： | LXT351QE |
| 廠商： | INTEL CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|QFP|44PIN|PLASTIC |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 1132K |
| 代理商： | LXT351QE |
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LXT351
—
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
20
Datasheet
2.5.2.2
Quasi-Random Signal Source (QRSS)
See
Figure 10
. For T1 operation, the Quasi-Random Signal Source (QRSS) is a 2
20
-1 pseudo-
random bit sequence (PRBS) with no more than 14 consecutive zeros. For E1 operation, QRSS is
2
15
-1 PRBS with inverted output. Setting bits CR2.EPAT0 = 0 and CR2.EPAT1 = 1 enables this
function.
The QRSS pattern is normally locked to TCLK; but if there is no TCLK, MCLK is the clock
source. Bellcore Pub 62411 defines the T1 QRSS transmit format and ITU G.703 defines the E1
format.
With QRSS transmission enabled, it is possible to insert a logic error into the transmit data stream
by causing a Low-to-High transition on INSLER. However, if no logic or bit errors are to be
inserted into the QRSS pattern, INSLER must remain Low. Logic Error insertion waits until the
next bit if the current bit is
“
jammed
”
. When there are more than 14 consecutive 0s, the output is
jammed to a 1.
Furthermore, a bipolar violation in the QRSS pattern is possible by causing a Low-to-High
transition on the INSBPV pin, regardless of whether the device is in Bipolar or Unipolar mode.
Choosing QRSS mode also enables the QRSS Pattern Detection in the receive path. The QRSS
pattern is synchronized when there are fewer than four errors in 128 bits. The PSR.QRSS bit
provides an indication of QRSS pattern synchronization. This bit goes Low when no QRSS pattern
detected (
i
.
e
., when there are more than four errors in 128 bits). The TQRSS bit in the Transition
Status Register indicates that QRSS status has changed since the last QRSS Interrupt Clear
command.
The LXT351 can generate an interrupt to indicate that QRSS detection has occurred, or that
synchronization is lost. The interrupt is enabled when ICR.CQRSS = 0.
Figure 9. TAOS Data Path
Figure 10. QRSS Mode
* If Enabled
INT*
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| LXT360 | 制造商:LVL1 制造商全稱:LVL1 功能描述:Integrated T1/E1 LH/SH Transceivers for DS1/DSX-1/CSU or NTU/ISDN PRI Applications |
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