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參數(shù)資料
| 型號(hào)： | LXT351QE |
| 廠商： | INTEL CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|QFP|44PIN|PLASTIC |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 26/46頁(yè) |
| 文件大?。?/td> | 1132K |
| 代理商： | LXT351QE |
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LXT351
—
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
26
Datasheet
4
ETAOS
1 = Enable Transmit All Ones
0 = Disable Transmit All Ones
5
EPAT0
Selects internal data pattern transmission. See
right hand section of table for codes.
6
EPAT1
7
RESET
1 = Reset device states and clear all registers.
0 = Reset complete.
Table 10. Control Register #3
Read/Write, Address (A7-A0) = x010010x
Bit
Name
Description
0
ESJAM
1 = Disable jamming of Elastic Store read out clock (
1
/
8
bit-time adjustment for over/underflow).
0 = Enable jamming of Elastic Store read out clock
1
ESCEN
1 = Center ES pointer for a difference of 16 or 32, depending on depth (clears automatically).
0 = Centering completed
2
ES64
1 = Set elastic store depth to 64 bits.
0 = Set elastic store depth to 32 bits.
3
-
Reserved. Set to 0 for normal operation.
4
EQZMON
1 = Configure receiver equalizer for monitor mode application (DSX-1 monitor).
0 = Configure receiver equalizer for normal mode application
5
SBIST
1 = Start Built-In Self Test.
0 = Built-In Self Test complete.
6
-
Reserved. Set to 0 for normal operation.
7
JA6HZ
1 = Set bandwidth of jitter attenuation loop to 6 Hz.
0 = Set bandwidth of jitter attenuation loop to 3 Hz.
Table 11. Interrupt Clear Register
Read/Write, Address (A7-A0) = x010011x
Bit
Name
Function
1
0
CLOS
1 = Clear/Mask Loss of Signal interrupt.
0 = Enable Loss of Signal interrupt.
1
-
Reserved. Set to 1 for normal operation.
2
CAIS
1 = Clear/Mask Alarm Indication Signal interrupt.
0 = Enable Alarm Indication Signal interrupt.
3
CQRSS
1 = Clear/Mask Quasi-Random Signal Source interrupt.
0 = Enable Quasi-Random Signal Source interrupt.
4
-
Reserved. Set to 1 for normal operation.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
Table 9. Control Register #2
Read/Write, Address (A7-A0) = x010001x
Bit
Name
Function
Pattern
EPAT0
EPAT1
Selected
1. To enable Dual loopback (DLOOP), set both ERLOOP = 1 and ELLOOP = 1.
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