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參數(shù)資料
| 型號(hào)： | LXT351QE |
| 廠商： | INTEL CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|QFP|44PIN|PLASTIC |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 37/46頁(yè) |
| 文件大?。?/td> | 1132K |
| 代理商： | LXT351QE |
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
—
LXT351
Datasheet
37
Table 26. Master and Transmit Clock Timing Characteristics for T1 Operation
(See Figure 14)
Parameter
Sym
Min
Typ
1
Max
Unit
Notes
Master clock frequency
MCLK
–
1.544
–
MHz
must be supplied
Master clock tolerance
MCLKt
–
±32
–
ppm
Master clock duty cycle
MCLKd
40
–
60
%
Transmit clock frequency
TCLK
–
1.544
–
MHz
Transmit clock tolerance
TCLKt
–
–
±100
ppm
Transmit clock duty cycle
TCLKd
10
–
90
%
TPOS/TNEG to TCLK setup time
t
SUT
50
–
–
ns
TCLK to TPOS/TNEG hold time
t
HT
50
–
–
ns
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Table 27. Master and Transmit Clock Timing Characteristics for E1 Operation
(See Figure 14)
Parameter
Sym
Min
Typ
1
Max
Unit
Notes
Master clock frequency
MCLK
–
2.048
–
MHz
must be supplied
Master clock tolerance
MCLKt
–
±32
–
ppm
Master clock duty cycle
MCLKd
40
–
60
%
Transmit clock frequency
TCLK
–
2.048
–
MHz
Transmit clock tolerance
TCLKt
–
–
±100
ppm
Transmit clock duty cycle
TCLKd
10
–
90
%
TPOS/TNEG to TCLK setup time
t
SUT
50
–
–
ns
TCLK to TPOS/TNEG hold time
t
HT
50
–
–
ns
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Figure 14. Transmit Clock Timing
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| LXT360 | 制造商:LVL1 制造商全稱:LVL1 功能描述:Integrated T1/E1 LH/SH Transceivers for DS1/DSX-1/CSU or NTU/ISDN PRI Applications |
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