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參數(shù)資料
| 型號： | LXT6234 |
| 廠商： | Intel Corp. |
| 英文描述： | E-Rate Multiplexer |
| 中文描述： | 電子速率復(fù)用器 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 327K |
| 代理商： | LXT6234 |
LXT6234
—
E-Rate Multiplexer
10
Datasheet
DLDNO1
85
HDB3 Encoder #1 Output -.
HDB3 Encoder #1 negative rail output clocked out on the rising edge of
DLCI1.
DLDPO2
88
HDB3 Encoder #2 Output +.
HDB3 Encoder #2 positive rail output clocked out on the rising edge of
DLCI2.
DLDNO2
89
HDB3 Encoder #2 Output -.
HDB3 Encoder #2 negative rail output clocked out on the rising edge of
DLCI2.
DLDPO3
94
HDB3 Encoder #3 Output +.
HDB3 Encoder #3 positive rail output clocked out on the rising edge of
DLCI3.
DLDNO3
95
HDB3 Encoder #3 Output -.
HDB3 Encoder #3 negative rail output clocked out on the rising edge of
DLCI3.
DLDPO4
98
HDB3 Encoder #4 Output +.
HDB3 Encoder #4 positive rail output clocked out on the rising edge of
DLCI4.
DLDNO4
99
HDB3 Encoder #4 Output -.
HDB3 Encoder #4 negative rail output clocked out on the rising edge of
DLCI4.
DHNRZO
52
HDB3 Decoder #5 NRZ Data Output.
HDB3 Decoder #5 NRZ data clocked out on the rising edge of
DHHDB3C.
DHBPV
53
HDB3 Decoder #5 Bipolar Violation Alarm.
This active high signal pulses every time a bipolar
violation occurs in the decoding process.
AUXO1
78
Auxiliary Flag/Data #1 Output.
Auxiliary Data #1 output that contains data value input on AUXI1. See
AUXI1 Description.
AUXO2
79
Auxiliary Flag/Data #2 Output.
Auxiliary Data #2 output that contains data value input on AUXI2. See
AUXI1 Description.
AUXO3
80
Auxiliary Flag/Data #3 Output.
Auxiliary Data #3 output that contains data value input on AUXI3. See
AUXI1 Description.
AUXO4
81
Auxiliary Flag/Data #4 Output.
Auxiliary Data #4 output that contains data value input on AUXI4. See
AUXI1 Description.
DNAT
62
National Bit Output.
Updated every frame based on the contents of the 12th bit in the frame as per
ITU G.742, G.751
DHAISD
58
Demultiplexer Input AIS Detect.
Active high alarm occurs when an all 1
’
s condition (AIS) is detected
at the DHNRZI input. This alarm will not occur if the input is a framed signal (i.e. all tributaries are AIS
on multiplexer side).
FLOS
59
Demultiplexer Loss of Frame Alarm.
Active high Frame Loss Alarm that occurs when the Demux
has not detected the Frame word.
MSYNC
38
Multiplexer Frame Sync Pulse.
Pulse of one high speed clock cycle synchronous with the last bit of
the frame (just before the frame word of the next frame).
DSYNC
55
Dmx Frame Sync Pulse.
Pulse of one high speed clock cycle synchronous with the first bit of the
frame word of the high speed incoming signal.
DAIS
61
AIS Error Bit Output.
Updated every frame based on the contents of the 11th bit in the frame as per
ITU G.742 and G.751.
NC
31, 43
51
Not Connected.
These pins must be left unconnected.
Table 2. Output Signals (Continued)
Sym
Pin #
Description
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| LXT6251A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
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