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參數(shù)資料
| 型號： | LXT6234 |
| 廠商： | Intel Corp. |
| 英文描述： | E-Rate Multiplexer |
| 中文描述： | 電子速率復(fù)用器 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 327K |
| 代理商： | LXT6234 |
E-Rate Multiplexer
—
LXT6234
Datasheet
11
3.0
Functional Description
The LXT6234 E-Rate Multiplexer consists of a multiplexer block, a demultiplexer block, five
HDB3 decoders, and five HDB3 encoders. If the HDB3 codecs are used, the signal flow would be
as follows:
Multiplexer:
Four tributaries of data feed HDB3 decoders one through four. The NRZ outputs of
the decoders are connected to the multiplexer tributary inputs. Within the multiplexer, the
justification or stuffing for each tributary is determined; the frame word is added; and the high
speed NRZ data sent out. The multiplexer output is connected to HDB3 encoder five where it is
encoded and sent out as Positive Data Output (MHDPO) and Negative Data Output (MHDNO).
Demultiplexer:
High speed encoded data feeds the HDB3 decoder five and is output as NRZ data.
The decoder output is connected to the demultiplexer input where it enters both the frame search
circuitry and the demultiplexing circuitry. Once the frame is detected, the NRZ data is
demultiplexed into the four tributaries and the justification is removed. Tributary data is then sent
out in NRZ format. These tributary outputs, both Clock Output (DLCO
x
) and NRZ Output
(DLNRZO
x
), are connected to HDB3 encoders one through four, encoded, and output as Positive
Data (MHDPO) and Negative Data (MHDNO).
3.1
Frame Format
The multiplexer and demultiplexer share the Mode Select (MODE) control pin. When MODE is
low, the multiplexer conforms to the ITU G.742 format for four-E1 to E2 (
Figure 4
). An E2 frame
is 848 bits long, with 205 data bits and one justification bit for each E1 tributary. When MODE is
high, the multiplexer conforms to the ITU G.751 format for four-E2 to E3 (
Figure 5
). This E3
frame is 1536 bits long, with 377 data bits and one justification bit for each E2 tributary.
In both E2 and E3 formats, there are two flag bits per frame: the AIS bit and the National bit. The
four justification bits may also be used as additional flag bits.
3.2
HDB3 Codecs
Five HDB3 codecs are included within the LXT6234 to allow easy integration with a wide range of
line interface circuits. There are four low speed codecs for the tributary streams and one high speed
codec to process the high speed output data. All five codecs are identical and all I/O pins are
externally accessible for each device. All codecs can be operated at the maximum operating speed
if the chip is used as a stand alone HDB3 transcoder. Note that the "low speed" decoders share a
clock with the multiplexer tributary clocks.
Each HDB3 decoder is provided with Positive Data, Negative Data, and clock; they decode the
data into a single NRZ bit stream. The HDB3 encoders are provided with NRZ data and clock; they
produce the Positive Data and Negative Data bit streams.
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