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參數(shù)資料
| 型號： | LXT6234 |
| 廠商： | Intel Corp. |
| 英文描述： | E-Rate Multiplexer |
| 中文描述： | 電子速率復用器 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 327K |
| 代理商： | LXT6234 |
E-Rate Multiplexer
—
LXT6234
Datasheet
17
5.0
Application Information
5.1
E1/E3 Multiplexer Block Diagram
Figure 7
is a block diagram of the E1/E3 Multiplexer.
5.1.1
E1 Line Interface
Receive clocks from the pulse data.
Pass either HDB3 encoded signals to the E-Rate Multiplexer as clock and RZ data or as NRZ
data
1
. (Both positive and negative RZ data.)
5.1.2
LXT6234, E1/E2 Stage
The LXT6234 may interface with either HDB3 or non-HDB3 coded signals. Data from an LIU
that does not perform HDB3 decoding must be connected to the HDB3 inputs on the
LXT6234. These are the clock (MLCK
x
) and decoder data input signals (both positive -
MLDP
x
and negative - MLDN
x
). When receiving data from an LIU which does perform
HDB3 decoding, the NRZ data is connected to the MLNRZx input and the clock connects to
the MLCK
x
in on the LXT6234
The four tributaries are interleaved into a single, intermediary E2 rate data stream. An
on-board crystal oscillator drives the data output frequency from the mux at the E2 rate of
8.448 MHz. A bit stuffing algorithm implemented in the LXT6234 ensures tributary rate
integrity at the output. The LXT6234 contains elastic store buffers to manage bit-stuffing
process.
The NRZ data is sent to a tributary of the E-Rate Multiplexer, stage E2/E3.
Figure 7. E1/E3 Multiplexer Block Diagram
t
su
t
h
t
pd
t
cy
MLCK
x
MHHDB3C
DLCI
x
DHHB3C
MLDPI
x
MHNRZI
DHDNI
MLNRZO
x
MHDPO
DHNRZO
DLDPO
x
t
pw
MLDNIx
DHDPI
DLNRZI
x
MLBPV
x
MHDNO
DHBPV
DLDNO
x
1.
If the HDB3 decoder is on the line interface unit (LIU).
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