參數(shù)資料
型號(hào)： M13S128324A
廠商： Elite Semiconductor Memory Technology Inc.
英文描述： 1M x 32 Bit x 4 Banks Double Data Rate SDRAM
中文描述： 100萬(wàn)× 32位× 4個(gè)銀行雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 11/49頁(yè)
文件大?。?/td> 888K
代理商： M13S128324A
ES MT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8 11/49
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the register is not defined, therefore the mode register must be written after
EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS ,
WE
and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The
state of address pins A0~A11 in the same cycle as CS , RAS , CAS ,
WE
and BA0 going low is written in the mode register.
Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The
mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3,
CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be
set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS
latencies.
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
Mode Register
A8
DLL Reset
A7
Mode
A3
Burst Type
0
No
0
Normal
0
Sequential
1
Yes
1
Test
1
Interleave
Burst Length
CAS Latency
A6
0
0
0
0
1
1
1
1
Latency
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Latency
Reserve
Reserve
2
3
4
Reserve
2.5
Reserve
A2
A1
A0
Sequential Interleave
Reserve
2
4
8
Reserve
Reserve
Reserve
Full Page
BA1 BA0
0
0
Operating Mode
MRS Cycle
EMRS Cycle
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
0
1
相關(guān)PDF資料
PDF描述
M13S2561616A 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A-4TG 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A-5TG 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A-6TG 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S256328A 2M x 32 Bit x 4 Banks Double Data Rate SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M13S128324A_09 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A_1 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-3.6BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-4BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-4LG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
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