參數(shù)資料
型號: M13S128324A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 1M x 32 Bit x 4 Banks Double Data Rate SDRAM
中文描述: 100萬× 32位× 4個銀行雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 17/49頁
文件大?。?/td> 888K
代理商: M13S128324A
ES MT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8 17/49
Burst Write Operation
The Burst Write command is issued by having CS , CAS and
WE
low while holding RAS high at the rising edge of the
clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for
burst write cycle. The first data of a burst write cycle must be applied on the DQ pins t
DS
(Data-in setup time) prior to data
strobe edge enabled after t
DQSS
from the rising edge of the clock (CLK) that the write command is issued. The remaining data
inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When
the burst has been finished, any additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
CO MM AN D
DQS
DQ 's
NOP
W RITE
NOP
NOP
NOP
NOP
NOP
NOP
t
D Q S S
t
W P S T
D i n 0
D i n 1
D i n 2
D i n 3
t
W P R E S
C L K
C L K
t
D S H
t
D S S
NOP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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M13S128324A-3.6BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-4BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-4LG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM